ext_imms_scaled (const struct ia64_operand *self, ia64_insn code,
ia64_insn *valuep, int scale)
{
- int i, bits = 0, total = 0, shift;
- BFD_HOST_64_BIT val = 0;
+ int i, bits = 0, total = 0;
+ BFD_HOST_64_BIT val = 0, sign;
for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
{
total += bits;
}
/* sign extend: */
- shift = 8*sizeof (val) - total;
- val = (val << shift) >> shift;
+ sign = (BFD_HOST_64_BIT) 1 << (total - 1);
+ val = (val ^ sign) - sign;
*valuep = (val << scale);
return 0;
static const char*
ins_immsu4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
- if (value == (BFD_HOST_U_64_BIT) 0x100000000)
- value = 0;
- else
- value = (((BFD_HOST_64_BIT)value << 32) >> 32);
+ value = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
return ins_imms_scaled (self, value, code, 0);
}
ins_immsm1u4 (const struct ia64_operand *self, ia64_insn value,
ia64_insn *code)
{
- if (value == (BFD_HOST_U_64_BIT) 0x100000000)
- value = 0;
- else
- value = (((BFD_HOST_64_BIT)value << 32) >> 32);
+ value = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
--value;
return ins_imms_scaled (self, value, code, 0);
{
/* constants: */
{ CST, ins_const, ext_const, "NIL", {{ 0, 0}}, 0, "<none>" },
+ { CST, ins_const, ext_const, "ar.csd", {{ 0, 0}}, 0, "ar.csd" },
{ CST, ins_const, ext_const, "ar.ccv", {{ 0, 0}}, 0, "ar.ccv" },
{ CST, ins_const, ext_const, "ar.pfs", {{ 0, 0}}, 0, "ar.pfs" },
{ CST, ins_const, ext_const, "1", {{ 0, 0}}, 0, "1" },
"a branch target" },
{ REL, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* TGT64 */
"a branch target" },
+
+ { ABS, ins_const, ext_const, 0, {{0, 0}}, 0, /* LDXMOV */
+ "ldxmov target" },
};