value += addend;
/* HIT_DATA is the address for the first byte for the relocated
- value. Subtract 1 so that we can manipulate the data in 32bit
+ value. Subtract 1 so that we can manipulate the data in 32-bit
hunks. */
hit_data--;
/* Retrieve the type byte for value from the section contents. */
value |= (bfd_get_32 (input_bfd, hit_data) & 0xff000000);
- /* Now scribble it out in one 32bit hunk. */
+ /* Now scribble it out in one 32-bit hunk. */
bfd_put_32 (input_bfd, value, hit_data);
return bfd_reloc_ok;
mov.b:16 -> mov.b:8 2 bytes
mov.b:24/32 -> mov.b:8 4 bytes
+ bset:24/32 -> bset:16 2 bytes
+ (also applicable to other bit manipulation instructions)
+
mov.[bwl]:24/32 -> mov.[bwl]:16 2 bytes */
static bfd_boolean
the linker is run. */
switch (ELF32_R_TYPE (irel->r_info))
{
- /* Try to turn a 24 bit absolute branch/call into an 8 bit
+ /* Try to turn a 24-bit absolute branch/call into an 8-bit
pc-relative branch/call. */
case R_H8_DIR24R8:
{
}
if (code == 0x5e)
+ /* This is jsr. */
bfd_put_8 (abfd, 0x55, contents + irel->r_offset - 1);
else if (code == 0x5a)
+ /* This is jmp. */
bfd_put_8 (abfd, 0x40, contents + irel->r_offset - 1);
else
abort ();
break;
}
- /* Try to turn a 16bit pc-relative branch into a 8bit pc-relative
+ /* Try to turn a 16-bit pc-relative branch into a 8-bit pc-relative
branch. */
case R_H8_PCREL16:
{
if (code == 0x58)
{
/* bCC:16 -> bCC:8 */
- /* Get the condition code from the original insn. */
+ /* Get the second byte of the original insn, which
+ contains the condition code. */
code = bfd_get_8 (abfd, contents + irel->r_offset - 1);
+
+ /* Compute the fisrt byte of the relaxed
+ instruction. The original sequence 0x58 0xX0
+ is relaxed to 0x4X, where X represents the
+ condition code. */
code &= 0xf0;
code >>= 4;
code |= 0x40;
bfd_put_8 (abfd, code, contents + irel->r_offset - 2);
}
else if (code == 0x5c)
+ /* This is bsr. */
bfd_put_8 (abfd, 0x55, contents + irel->r_offset - 2);
else
abort ();
}
}
- /* Fall through. */
+ /* Fall through. */
+
+ /* This is a 24-/32-bit absolute address in one of the
+ following instructions:
+
+ "band", "bclr", "biand", "bild", "bior", "bist",
+ "bixor", "bld", "bnot", "bor", "bset", "bst", "btst",
+ "bxor", "ldc.w", "stc.w" and "mov.[bwl]"
- /* This is a 24/32bit absolute address in a "mov" insn, which may
- become a 16-bit absolute address if it is in the right range. */
+ We may relax this into an 16-bit absolute address if it's
+ in the right range. */
case R_H8_DIR32A16:
{
bfd_vma value;
/* Get the opcode. */
code = bfd_get_8 (abfd, contents + irel->r_offset - 1);
- /* We just need to turn off bit 0x20. */
+ /* Fix the opcode. For all the instructions that
+ belong to this relaxation, we simply need to turn
+ off bit 0x20 in the previous byte. */
code &= ~0x20;
bfd_put_8 (abfd, code, contents + irel->r_offset - 1);