Check reloc against IFUNC symbol only with dynamic symbols

[deliverable/binutils-gdb.git] / bfd / elf32-rl78.c

diff --git a/bfd/elf32-rl78.c b/bfd/elf32-rl78.c
index add3336ee7beaad92b298e0539b0120ac644f645..b6e0eb8f92332bc2a86004547349dd9120bad13e 100644 (file)
--- a/bfd/elf32-rl78.c
+++ b/bfd/elf32-rl78.c
@@ -1,5 +1,5 @@
 /* Renesas RL78 specific support for 32-bit ELF.
-   Copyright (C) 2011-2015 Free Software Foundation, Inc.
+   Copyright (C) 2011-2016 Free Software Foundation, Inc.
 
    This file is part of BFD, the Binary File Descriptor library.
 
@@ -448,7 +448,7 @@ rl78_compute_complex_reloc (unsigned long  r_type,
     case R_RL78_SYM:
       RL78_STACK_PUSH (symval);
       return 0;
-      
+
     case R_RL78_OPneg:
       RL78_STACK_POP (tmp1);
       tmp1 = - tmp1;
@@ -758,7 +758,7 @@ rl78_elf_relocate_section
        RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
                                         rel, 1, relend, howto, 0, contents);
 
-      if (info->relocatable)
+      if (bfd_link_relocatable (info))
        {
          /* This is a relocatable link.  We don't have to change
              anything, unless the reloc is against a section symbol,
@@ -1046,7 +1046,7 @@ rl78_elf_relocate_section
              break;
            }
          break;
-         
+
        case R_RL78_SYM:
          if (r_symndx < symtab_hdr->sh_info)
            relocation = sec->output_section->vma + sec->output_offset
@@ -1244,7 +1244,7 @@ rl78_elf_merge_private_bfd_data (bfd * ibfd, bfd * obfd)
            (*_bfd_error_handler) (_("- %s is 64-bit, %s is not"),
                                   bfd_get_filename (ibfd), bfd_get_filename (obfd));
          error = TRUE;
-       }    
+       }
     }
 
   return !error;
@@ -1310,7 +1310,7 @@ rl78_elf_check_relocs
   asection *splt;
   bfd *dynobj;
 
-  if (info->relocatable)
+  if (bfd_link_relocatable (info))
     return TRUE;
 
   symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
@@ -1442,7 +1442,7 @@ rl78_elf_always_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
   bfd *dynobj;
   asection *splt;
 
-  if (info->relocatable)
+  if (bfd_link_relocatable (info))
     return TRUE;
 
   dynobj = elf_hash_table (info)->dynobj;
@@ -1529,7 +1529,7 @@ rl78_elf_relax_plt_section (bfd *dynobj,
   /* Assume nothing changes.  */
   *again = FALSE;
 
-  if (info->relocatable)
+  if (bfd_link_relocatable (info))
     return TRUE;
 
   /* We only relax the .plt section at the moment.  */
@@ -1971,10 +1971,18 @@ rl78_offset_for_reloc (bfd *                    abfd,
        case R_RL78_ABS8UW:
          *scale = 2;
          goto reloc_computes_value;
-         
+
        default:
        reloc_computes_value:
-         symval = rl78_compute_complex_reloc (r_type, 0, input_section);
+         symval = rl78_compute_complex_reloc (r_type, symval, input_section);
+       case R_RL78_DIR32:
+       case R_RL78_DIR24S:
+       case R_RL78_DIR16:
+       case R_RL78_DIR16U:
+       case R_RL78_DIR16S:
+       case R_RL78_DIR24S_PCREL:
+       case R_RL78_DIR16S_PCREL:
+       case R_RL78_DIR8S_PCREL:
          if (lrel)
            *lrel = rel;
          return symval;
@@ -2088,14 +2096,17 @@ rl78_elf_relax_section
   /* We don't have to do anything for a relocatable link, if
      this section does not have relocs, or if this is not a
      code section.  */
-  if (link_info->relocatable
+  if (bfd_link_relocatable (link_info)
       || (sec->flags & SEC_RELOC) == 0
       || sec->reloc_count == 0
       || (sec->flags & SEC_CODE) == 0)
     return TRUE;
 
-  symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
-  shndx_hdr = &elf_tdata (abfd)->symtab_shndx_hdr;
+  symtab_hdr = & elf_symtab_hdr (abfd);
+  if (elf_symtab_shndx_list (abfd))
+    shndx_hdr = & elf_symtab_shndx_list (abfd)->hdr;
+  else
+    shndx_hdr = NULL;
 
   /* Get the section contents.  */
   if (elf_section_data (sec)->this_hdr.contents != NULL)
@@ -2118,7 +2129,7 @@ rl78_elf_relax_section
       symtab_hdr->contents = (bfd_byte *) intsyms;
     }
 
-  if (shndx_hdr->sh_size != 0)
+  if (shndx_hdr && shndx_hdr->sh_size != 0)
     {
       bfd_size_type amt;
 
@@ -2313,6 +2324,27 @@ rl78_elf_relax_section
 
          switch (insn[0])
            {
+           case 0xdc: /* BC */
+           case 0xdd: /* BZ */
+           case 0xde: /* BNC */
+           case 0xdf: /* BNZ */
+             if (insn[1] == 0x03 && insn[2] == 0xee /* BR */
+                 && (srel->r_offset - irel->r_offset) > 1) /* a B<c> without its own reloc */
+               {
+                 /* This is a "long" conditional as generated by gas:
+                    DC 03 EE ad.dr  */
+                 if (pcrel < 127
+                     && pcrel > -127)
+                   {
+                     insn[0] ^= 0x02; /* invert conditional */
+                     SNIPNR (4, 1);
+                     SNIP (1, 2, R_RL78_DIR8S_PCREL);
+                     insn[1] = pcrel;
+                     *again = TRUE;
+                   }
+               }
+             break;
+
            case 0xec: /* BR !!abs20 */
 
              if (pcrel < 127
@@ -2328,7 +2360,7 @@ rl78_elf_relax_section
                  insn[0] = 0xed;
                  insn[1] = symval & 0xff;
                  insn[2] = symval >> 8;
-                 SNIP (2, 1, R_RL78_DIR16S);
+                 SNIP (2, 1, R_RL78_DIR16U);
                  *again = TRUE;
                }
              else if (pcrel < 32767
@@ -2360,7 +2392,7 @@ rl78_elf_relax_section
                  insn[0] = 0xfd;
                  insn[1] = symval & 0xff;
                  insn[2] = symval >> 8;
-                 SNIP (2, 1, R_RL78_DIR16S);
+                 SNIP (2, 1, R_RL78_DIR16U);
                  *again = TRUE;
                }
              else if (pcrel < 32767
@@ -2383,6 +2415,25 @@ rl78_elf_relax_section
                 here anyway. */
              switch (insn[1])
                {
+               case 0xd3: /* BNH */
+               case 0xc3: /* BH */
+                 if (insn[2] == 0x03 && insn[3] == 0xee
+                     && (srel->r_offset - irel->r_offset) > 2) /* a B<c> without its own reloc */
+                   {
+                     /* Another long branch by gas:
+                        61 D3 03 EE ad.dr  */
+                     if (pcrel < 127
+                         && pcrel > -127)
+                       {
+                         insn[1] ^= 0x10; /* invert conditional */
+                         SNIPNR (5, 1);
+                         SNIP (2, 2, R_RL78_DIR8S_PCREL);
+                         insn[2] = pcrel;
+                         *again = TRUE;
+                       }
+                   }
+                 break;
+
                case 0xc8: /* SKC */
                  if (insn[2] == 0xef)
                    {