/* RISC-V-specific support for NN-bit ELF.
- Copyright 2011-2016 Free Software Foundation, Inc.
+ Copyright (C) 2011-2017 Free Software Foundation, Inc.
Contributed by Andrew Waterman (andrew@sifive.com).
Based on TILE-Gx and MIPS targets.
/* PR15323, ref flags aren't set for references in the same
object. */
- h->root.non_ir_ref = 1;
+ h->root.non_ir_ref_regular = 1;
}
switch (r_type)
to copy the initial value out of the dynamic object and into the
runtime process image. We need to remember the offset into the
.rel.bss section we are going to use. */
- if ((h->root.u.def.section->flags & SEC_READONLY) != 0)
+ if (eh->tls_type & ~GOT_NORMAL)
+ {
+ s = htab->sdyntdata;
+ srel = htab->elf.srelbss;
+ }
+ else if ((h->root.u.def.section->flags & SEC_READONLY) != 0)
{
s = htab->elf.sdynrelro;
srel = htab->elf.sreldynrelro;
h->needs_copy = 1;
}
- if (eh->tls_type & ~GOT_NORMAL)
- return _bfd_elf_adjust_dynamic_copy (info, h, htab->sdyntdata);
-
return _bfd_elf_adjust_dynamic_copy (info, h, s);
}
{
struct bfd_link_hash_entry *h;
- h = bfd_link_hash_lookup (info->hash, "_gp", FALSE, FALSE, TRUE);
+ h = bfd_link_hash_lookup (info->hash, RISCV_GP_SYMBOL, FALSE, FALSE, TRUE);
if (h == NULL || h->type != bfd_link_hash_defined)
return 0;
case R_RISCV_SET8:
case R_RISCV_SET16:
case R_RISCV_SET32:
+ case R_RISCV_32_PCREL:
case R_RISCV_TLS_DTPREL32:
case R_RISCV_TLS_DTPREL64:
break;
case R_RISCV_SET8:
case R_RISCV_SET16:
case R_RISCV_SET32:
+ case R_RISCV_32_PCREL:
/* These require no special handling beyond perform_relocation. */
break;
rela.r_offset = sec_addr (h->root.u.def.section) + h->root.u.def.value;
rela.r_info = ELFNN_R_INFO (h->dynindx, R_RISCV_COPY);
rela.r_addend = 0;
- if ((h->root.u.def.section->flags & SEC_READONLY) != 0)
+ if (h->root.u.def.section == htab->elf.sdynrelro)
s = htab->elf.sreldynrelro;
else
s = htab->elf.srelbss;
ret = riscv_finish_dyn (output_bfd, info, dynobj, sdyn);
- if (ret != TRUE)
+ if (!ret)
return ret;
/* Fill in the head and tail entries in the procedure linkage table. */
for (i = 0; i < PLT_HEADER_INSNS; i++)
bfd_put_32 (output_bfd, plt_header[i], splt->contents + 4*i);
- }
- elf_section_data (splt->output_section)->this_hdr.sh_entsize
- = PLT_ENTRY_SIZE;
+ elf_section_data (splt->output_section)->this_hdr.sh_entsize
+ = PLT_ENTRY_SIZE;
+ }
}
if (htab->elf.sgotplt)
BFD_ASSERT (rel->r_offset + 4 <= sec->size);
+ if (gp)
+ {
+ /* If gp and the symbol are in the same output section, then
+ consider only that section's alignment. */
+ struct bfd_link_hash_entry *h =
+ bfd_link_hash_lookup (link_info->hash, RISCV_GP_SYMBOL, FALSE, FALSE,
+ TRUE);
+ if (h->u.def.section->output_section == sym_sec->output_section)
+ max_alignment = (bfd_vma) 1 << sym_sec->output_section->alignment_power;
+ }
+
/* Is the reference in range of x0 or gp?
Valid gp range conservatively because of alignment issue. */
if (VALID_ITYPE_IMM (symval)
return TRUE;
}
+/* Set the right mach type. */
+static bfd_boolean
+riscv_elf_object_p (bfd *abfd)
+{
+ /* There are only two mach types in RISCV currently. */
+ if (strcmp (abfd->xvec->name, "elf32-littleriscv") == 0)
+ bfd_default_set_arch_mach (abfd, bfd_arch_riscv, bfd_mach_riscv32);
+ else
+ bfd_default_set_arch_mach (abfd, bfd_arch_riscv, bfd_mach_riscv64);
+
+ return TRUE;
+}
+
#define TARGET_LITTLE_SYM riscv_elfNN_vec
#define TARGET_LITTLE_NAME "elfNN-littleriscv"
#define elf_backend_plt_sym_val riscv_elf_plt_sym_val
#define elf_backend_grok_prstatus riscv_elf_grok_prstatus
#define elf_backend_grok_psinfo riscv_elf_grok_psinfo
+#define elf_backend_object_p riscv_elf_object_p
#define elf_info_to_howto_rel NULL
#define elf_info_to_howto riscv_info_to_howto_rela
#define bfd_elfNN_bfd_relax_section _bfd_riscv_relax_section