[AArch64] Workaround for Cortex A53 erratum 843419

[deliverable/binutils-gdb.git] / bfd / elfxx-aarch64.c

diff --git a/bfd/elfxx-aarch64.c b/bfd/elfxx-aarch64.c
index b513a548570035f9f0e7a7fe8d1f8df5f299fec6..db9d4fa01924342cbc110877d1ac06c7a389debc 100644 (file)
--- a/bfd/elfxx-aarch64.c
+++ b/bfd/elfxx-aarch64.c
@@ -25,6 +25,26 @@
 
 #define MASK(n) ((1u << (n)) - 1)
 
+/* Sign-extend VALUE, which has the indicated number of BITS.  */
+
+bfd_signed_vma
+_bfd_aarch64_sign_extend (bfd_vma value, int bits)
+{
+  if (value & ((bfd_vma) 1 << (bits - 1)))
+    /* VALUE is negative.  */
+    value |= ((bfd_vma) - 1) << bits;
+
+  return value;
+}
+
+/* Decode the IMM field of ADRP.  */
+
+uint32_t
+_bfd_aarch64_decode_adrp_imm (uint32_t insn)
+{
+  return (((insn >> 5) & MASK (19)) << 2) | ((insn >> 29) & MASK (2));
+}
+
 /* Reencode the imm field of add immediate.  */
 static inline uint32_t
 reencode_add_imm (uint32_t insn, uint32_t imm)
@@ -32,9 +52,10 @@ reencode_add_imm (uint32_t insn, uint32_t imm)
   return (insn & ~(MASK (12) << 10)) | ((imm & MASK (12)) << 10);
 }
 
-/* Reencode the imm field of adr.  */
-static inline uint32_t
-reencode_adr_imm (uint32_t insn, uint32_t imm)
+/* Reencode the IMM field of ADR.  */
+
+uint32_t
+_bfd_aarch64_reencode_adr_imm (uint32_t insn, uint32_t imm)
 {
   return (insn & ~((MASK (2) << 29) | (MASK (19) << 5)))
     | ((imm & MASK (2)) << 29) | ((imm & (MASK (19) << 2)) << 3);
@@ -220,7 +241,7 @@ _bfd_aarch64_elf_put_addend (bfd *abfd,
     case BFD_RELOC_AARCH64_ADR_LO21_PCREL:
     case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
     case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL:
-      contents = reencode_adr_imm (contents, addend);
+      contents = _bfd_aarch64_reencode_adr_imm (contents, addend);
       break;
 
     case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC: