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[deliverable/binutils-gdb.git] / cpu / ChangeLog

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+2020-06-02  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+       * bpf.cpu (define-bpf-isa): Set base-insn-bitsize to 64.
+       * bpf.opc (bpf_print_insn): Do not set endian_code here.
+
+2020-06-02  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+       * mep.opc (print_slot_insn): Pass the insn endianness to
+       cgen_get_insn_value.
+
+2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
+           David Faust <david.faust@oracle.com>
+
+       * bpf.cpu (define-alu-insn-un): Add definitions of semantics.
+       (define-alu-insn-mov): Likewise.
+       (daib): Likewise.
+       (define-alu-instructions): Likewise.
+       (define-endian-insn): Likewise.
+       (define-lddw): Likewise.
+       (dlabs): Likewise.
+       (dlind): Likewise.
+       (dxli): Likewise.
+       (dxsi): Likewise.
+       (dsti): Likewise.
+       (define-ldstx-insns): Likewise.
+       (define-st-insns): Likewise.
+       (define-cond-jump-insn): Likewise.
+       (dcji): Likewise.
+       (define-condjump-insns): Likewise.
+       (define-call-insn): Likewise.
+       (ja): Likewise.
+       ("exit"): Likewise.
+       (define-atomic-insns): Likewise.
+       (sem-exchange-and-add): New macro.
+       * bpf.cpu ("brkpt"): New instruction.
+       (bpfbf): Set word-bitsize to 32 and insn-endian big.
+       (h-gpr): Prefer r0 to `a' and r6 to `ctx'.
+       (h-pc): Expand definition.
+       * bpf.opc (bpf_print_insn): Set endian_code to BIG.
+
+2020-05-21  Alan Modra  <amodra@gmail.com>
+
+       * mep.opc (mep_cgen_expand_macros_and_parse_operand): Replace
+       "if (x) free (x)" with "free (x)".
+
+2020-05-19  Stafford Horne  <shorne@gmail.com>
+
+       PR 25184
+       * or1k.cpu (arch or1k): Remove or64 and or64nd machs.
+       (ORBIS-MACHS, ORFPX32-MACHS): Remove pmacros.
+       (cpu or1k64bf, mach or64, mach or64nd): Remove definitions.
+       * or1kcommon.cpu (h-fdr): Remove hardware.
+       * or1korfpx.cpu (rDDF, rADF, rBDF): Remove operand definitions.
+       (float-regreg-insn): Remove lf- mnemonic -d instruction pattern.
+       (float-setflag-insn-base): Remove lf-sf mnemonic -d pattern.
+       (float-cust-insn): Remove "lf-cust" cust-num "-d" pattern.
+       (lf-rem-d, lf-itof-d, lf-ftoi-d, lf-madd-d): Remove.
+
+2020-02-16  David Faust  <david.faust@oracle.com>
+
+       * bpf.cpu (define-cond-jump-insn): Renamed from djci.
+       (dcji) New version with support for JMP32
+
+2020-02-03  Alan Modra  <amodra@gmail.com>
+
+       * m32c.cpu (f-dsp-64-s16): Mask before shifting signed value.
+
+2020-02-01  Alan Modra  <amodra@gmail.com>
+
+       * frv.cpu (f-u12): Multiply rather than left shift signed values.
+       (f-label16, f-label24): Likewise.
+
+2020-01-30  Alan Modra  <amodra@gmail.com>
+
+       * m32c.cpu (f-src32-rn-unprefixed-QI): Shift before inverting.
+       (f-src32-rn-prefixed-QI, f-dst32-rn-unprefixed-QI): Likewise.
+       (f-dst32-rn-prefixed-QI): Likewise.
+       (f-dsp-32-s32): Mask before shifting left.
+       (f-dsp-48-u32, f-dsp-48-s32): Likewise.
+       (f-bitbase32-16-s11-unprefixed): Multiply signed field rather than
+       shifting left.
+       (f-bitbase32-24-s11-prefixed, f-bitbase32-24-s19-prefixed): Likewise.
+       (h-gr-SI): Mask before shifting.
+
+2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+       * bpf.cpu (define-alu-insn-un): The unary BPF instructions
+       (neg and neg32) use OP_SRC_K even if they operate only in
+       registers.
+
+2020-01-18  Nick Clifton  <nickc@redhat.com>
+
+       Binutils 2.34 branch created.
+
 2020-01-13  Alan Modra  <amodra@gmail.com>
 
        * fr30.cpu (f-disp9, f-disp10, f-s10, f-rel9, f-rel12): Don't