;; Whereas the 128-bit instructions (at the moment there is only one
;; of such instructions, lddw) have the form:
;;
-;; code:8 regs:8 offset:16 imm:32 imm:32 unused:32
+;; code:8 regs:8 offset:16 imm:32 unused:32 imm:32
;;
;; In both formats `regs' is itself composed by two fields:
;;
;; XXX the frame pointer fp is read-only, so it should
;; go in a different hardware.
(;; ABI names. Take priority when disassembling.
- (a 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (ctx 6)
+ (r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6)
(r7 7) (r8 8) (r9 9) (fp 10)
;; Additional names recognized when assembling.
- (r0 0) (r6 6) (r10 10))))
+ (a 0) (ctx 6) (r10 10))))
;; The program counter. CGEN requires it, even if it is not visible
;; to eBPF programs.
(define-normal-insn-enum insn-op-class "eBPF instruction class"
(all-isas) OP_CLASS_ f-op-class
((LD #b000) (LDX #b001) (ST #b010) (STX #b011)
- (ALU #b100) (JMP #b101) (ALU64 #b111)))
+ (ALU #b100) (JMP #b101) (JMP32 #b110) (ALU64 #b111)))
;; For load/store instructions, the 8-bit code field is subdivided in:
;;
(set (ifield f-imm64-a) (and (ifield f-imm64) (const #xffffffff)))))
(extract (sequence ()
(set (ifield f-imm64)
- (or (sll DI (zext DI (ifield f-imm64-c)) (const 32))
- (zext DI (ifield f-imm64-a)))))))
+ (or (sll UDI (zext UDI (ifield f-imm64-c)) (const 32))
+ (zext UDI (ifield f-imm64-a)))))))
;;; Operands
((ISA (.sym ebpf x-endian)))
(.str x-basename x-suffix " $dst" x-endian)
(+ (f-imm32 0) (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian)
- x-op-class OP_SRC_X x-op-code) () ()))
+ x-op-class OP_SRC_K x-op-code) () ()))
(define-pmacro (define-alu-insn-bin x-basename x-suffix x-op-class x-op-code x-endian)
(begin
(define-lddw le)
(define-lddw be)
-;; The absolute/indirect load instructions are non-generic loads
-;; designed to be used in socket filters. They come in several
-;; variants:
+;; The absolute load instructions are non-generic loads designed to be
+;; used in socket filters. They come in several variants:
;;
-;; LD{abs,ind}{w,h,b,dw}le for the little-endian ISA
-;; LD{abs,ind}[w,h,b,dw}be for the big-endian ISA
+;; LDABS{w,h,b,dw}
-(define-pmacro (dlsi x-basename x-suffix x-class x-size x-mode x-endian)
- (dni (.sym x-basename x-suffix x-endian)
- (.str x-basename x-suffix)
+(define-pmacro (dlabs x-suffix x-size)
+ (dni (.sym "ldabs" x-suffix)
+ (.str "ldabs" x-suffix)
+ (all-isas)
+ (.str "ldabs" x-suffix " $imm32")
+ (+ imm32 (f-offset16 0) (f-regs 0)
+ OP_CLASS_LD OP_MODE_ABS (.sym OP_SIZE_ x-size))
+ () ()))
+
+(dlabs "w" W)
+(dlabs "h" H)
+(dlabs "b" B)
+(dlabs "dw" DW)
+
+;; The indirect load instructions are non-generic loads designed to be
+;; used in socket filters. They come in several variants:
+;;
+;; LDIND{w,h,b,dw}le for the little-endian ISA
+;; LDIND[w,h,b,dw}be for the big-endian ISA
+
+(define-pmacro (dlind x-suffix x-size x-endian)
+ (dni (.sym "ldind" x-suffix x-endian)
+ (.str "ldind" x-suffix)
((ISA (.sym ebpf x-endian)))
- (.str x-basename x-suffix " $dst" x-endian ",$src" x-endian ",$imm32")
- (+ imm32 (f-offset16 0) (.sym src x-endian) (.sym dst x-endian)
- (.sym OP_CLASS_ x-class) (.sym OP_SIZE_ x-size)
- (.sym OP_MODE_ x-mode)) () ()))
+ (.str "ldind" x-suffix " $src" x-endian ",$imm32")
+ (+ imm32 (f-offset16 0) ((.sym f-dst x-endian) 0) (.sym src x-endian)
+ OP_CLASS_LD OP_MODE_IND (.sym OP_SIZE_ x-size))
+ () ()))
-(define-pmacro (define-ldabsind x-endian)
- (begin
- (dlsi "ldabs" "w" LD W ABS x-endian)
- (dlsi "ldabs" "h" LD H ABS x-endian)
- (dlsi "ldabs" "b" LD B ABS x-endian)
- (dlsi "ldabs" "dw" LD DW ABS x-endian)
-
- (dlsi "ldind" "w" LD W IND x-endian)
- (dlsi "ldind" "h" LD H IND x-endian)
- (dlsi "ldind" "b" LD B IND x-endian)
- (dlsi "ldind" "dw" LD DW IND x-endian)))
-
-(define-ldabsind le)
-(define-ldabsind be)
+(define-pmacro (define-ldind x-endian)
+ (begin
+ (dlind "w" W x-endian)
+ (dlind "h" H x-endian)
+ (dlind "b" B x-endian)
+ (dlind "dw" DW x-endian)))
+
+(define-ldind le)
+(define-ldind be)
;; Generic load and store instructions are provided for several word
;; sizes. They come in several variants:
;; registers. Therefore, we need to define several variants in both
;; ISAs:
;;
-;; J{eq,gt,ge,lt,le,set,ne,sgt,sge,slt,sle}{i,r}le for the
+;; J{eq,gt,ge,lt,le,set,ne,sgt,sge,slt,sle}[32]{i,r}le for the
;; little-endian ISA.
-;; J{eq,gt,ge,lt,le,set,ne.sgt,sge,slt,sle}{i,r}be for the
+;; J{eq,gt,ge,lt,le,set,ne.sgt,sge,slt,sle}[32]{i,r}be for the
;; big-endian ISA.
-(define-pmacro (dcji x-cond x-op-code x-endian)
+(define-pmacro (define-cond-jump-insn x-cond x-suffix x-op-class x-op-code x-endian)
(begin
- (dni (.sym j x-cond i x-endian)
- (.str j x-cond "i")
+ (dni (.sym j x-cond x-suffix i x-endian)
+ (.str j x-cond x-suffix " i")
((ISA (.sym ebpf x-endian)))
- (.str "j" x-cond " $dst" x-endian ",$imm32,$disp16")
+ (.str "j" x-cond x-suffix " $dst" x-endian ",$imm32,$disp16")
(+ imm32 disp16 ((.sym f-src x-endian) 0) (.sym dst x-endian)
- OP_CLASS_JMP OP_SRC_K (.sym OP_CODE_ x-op-code)) () ())
- (dni (.sym j x-cond r x-endian)
- (.str j x-cond "r")
+ x-op-class OP_SRC_K (.sym OP_CODE_ x-op-code)) () ())
+ (dni (.sym j x-cond x-suffix r x-endian)
+ (.str j x-cond x-suffix " r")
((ISA (.sym ebpf x-endian)))
- (.str "j" x-cond " $dst" x-endian ",$src" x-endian ",$disp16")
+ (.str "j" x-cond x-suffix " $dst" x-endian ",$src" x-endian ",$disp16")
(+ (f-imm32 0) disp16 (.sym src x-endian) (.sym dst x-endian)
- OP_CLASS_JMP OP_SRC_X (.sym OP_CODE_ x-op-code)) () ())))
+ x-op-class OP_SRC_X (.sym OP_CODE_ x-op-code)) () ())))
+
+(define-pmacro (dcji x-cond x-op-code x-endian)
+ (begin
+ (define-cond-jump-insn x-cond "" OP_CLASS_JMP x-op-code x-endian)
+ (define-cond-jump-insn x-cond "32" OP_CLASS_JMP32 x-op-code x-endian)))
(define-pmacro (define-condjump-insns x-endian)
(begin
projects / deliverable / binutils-gdb.git / blobdiff