(NEXTBYTE, NEXTWORD, NEXTLONG, NEXTULONG, NEXTSINGLE)

[deliverable/binutils-gdb.git] / cpu / m32c.cpu

diff --git a/cpu/m32c.cpu b/cpu/m32c.cpu
index 4c76afe31667754ba80da4194f0bf9dd0cceec7a..c5eedf33b219a19fbbd2ee700e38941a5ff9afb7 100644 (file)
--- a/cpu/m32c.cpu
+++ b/cpu/m32c.cpu
@@ -1,6 +1,6 @@
 ; Renesas M32C CPU description.  -*- Scheme -*-
 ;
-; Copyright 2005, 2006 Free Software Foundation, Inc.
+; Copyright 2005, 2006, 2007 Free Software Foundation, Inc.
 ;
 ; Contributed by Red Hat Inc; developed under contract from Renesas.
 ;
@@ -8,7 +8,7 @@
 ;
 ; This program is free software; you can redistribute it and/or modify
 ; it under the terms of the GNU General Public License as published by
-; the Free Software Foundation; either version 2 of the License, or
+; the Free Software Foundation; either version 3 of the License, or
 ; (at your option) any later version.
 ;
 ; This program is distributed in the hope that it will be useful,
@@ -18,7 +18,8 @@
 ;
 ; You should have received a copy of the GNU General Public License
 ; along with this program; if not, write to the Free Software
-; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+; MA 02110-1301, USA.
 
 (include "simplify.inc")
 
@@ -1939,7 +1940,7 @@
 )
 (define-full-operand Imm-8-s4n "negated 4 bit immediate at offset 8 bits" (all-isas)
   h-sint DFLT f-imm-8-s4
-  ((parse "signed4n")) () ()
+  ((parse "signed4n") (print "signed4n")) () ()
 )
 (define-full-operand Imm-sh-8-s4 "signed 4 bit shift immediate at offset 8 bits" (all-isas)
   h-shimm DFLT f-imm-8-s4
@@ -2146,9 +2147,9 @@
 (dnop Lab-8-16    "16 bit label" (all-isas RELAX) h-iaddr f-lab-8-16)
 (dnop Lab-8-24    "24 bit label" (all-isas RELAX) h-iaddr f-lab-8-24)
 (dnop Lab-16-8    "8 bit label"  (all-isas RELAX) h-iaddr f-lab-16-8)
-(dnop Lab-24-8    "8 bit label"  (all-isas) h-iaddr f-lab-24-8)
-(dnop Lab-32-8    "8 bit label"  (all-isas) h-iaddr f-lab-32-8)
-(dnop Lab-40-8    "8 bit label"  (all-isas) h-iaddr f-lab-40-8)
+(dnop Lab-24-8    "8 bit label"  (all-isas RELAX) h-iaddr f-lab-24-8)
+(dnop Lab-32-8    "8 bit label"  (all-isas RELAX) h-iaddr f-lab-32-8)
+(dnop Lab-40-8    "8 bit label"  (all-isas RELAX) h-iaddr f-lab-40-8)
 
 ;-------------------------------------------------------------
 ; Condition code bits
@@ -6681,7 +6682,7 @@
 (define-pmacro (arith-jnz-imm4-dst-defn mach src dstgroup label mode wstr op encoding sem)
   (dni (.sym op mach wstr - imm4 - dstgroup)
        (.str op wstr " " mach "-imm4-" dstgroup "-" label "-" mode)
-       ((machine mach))
+       (RL_JUMP RELAXABLE (machine mach))
        (.str op wstr " #${" src "},${dst" mach "-" dstgroup "-" mode "},${" label "}")
        encoding
        (sem mode src (.sym dst mach - dstgroup - mode) label)
@@ -6695,10 +6696,10 @@
                             (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-basic- mode) Lab-16-8)
                             sem)
     (arith-jnz-imm4-dst-defn 16 (.sym Imm-8- i4n) 16-16 Lab-32-8 mode wstr op
-                            (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-16-16- mode) Lab-16-8)
+                            (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-16-16- mode) Lab-32-8)
                             sem)
     (arith-jnz-imm4-dst-defn 16 (.sym Imm-8- i4n) 16-8 Lab-24-8 mode wstr op
-                            (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-16-8- mode) Lab-16-8)
+                            (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-16-8- mode) Lab-24-8)
                             sem)
   )
 )