clk: qcom: Introduce parent_map tables

[deliverable/linux.git] / drivers / clk / qcom / clk-rcg.h

diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index 687e41f91d7c9f90d99eb80acbd98086d237e4e5..56028bb31d8713f4a627a78027191df58b504bfb 100644 (file)
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -25,6 +25,16 @@ struct freq_tbl {
        u16 n;
 };
 
+/**
+ * struct parent_map - map table for PLL source select configuration values
+ * @src: source PLL
+ * @cfg: configuration value
+ */
+struct parent_map {
+       u8 src;
+       u8 cfg;
+};
+
 /**
  * struct mn - M/N:D counter
  * @mnctr_en_bit: bit to enable mn counter
@@ -65,7 +75,7 @@ struct pre_div {
 struct src_sel {
        u8              src_sel_shift;
 #define SRC_SEL_MASK   0x7
-       const u8        *parent_map;
+       const struct parent_map *parent_map;
 };
 
 /**
@@ -96,6 +106,7 @@ struct clk_rcg {
 
 extern const struct clk_ops clk_rcg_ops;
 extern const struct clk_ops clk_rcg_bypass_ops;
+extern const struct clk_ops clk_rcg_lcc_ops;
 
 #define to_clk_rcg(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg, clkr)
 
@@ -150,7 +161,7 @@ struct clk_rcg2 {
        u32                     cmd_rcgr;
        u8                      mnd_width;
        u8                      hid_width;
-       const u8                *parent_map;
+       const struct parent_map *parent_map;
        const struct freq_tbl   *freq_tbl;
        struct clk_regmap       clkr;
 };