#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>
+enum sh_tmu_model {
+ SH_TMU_LEGACY,
+ SH_TMU,
+ SH_TMU_SH3,
+};
+
struct sh_tmu_device;
struct sh_tmu_channel {
struct sh_tmu_device *tmu;
+ unsigned int index;
void __iomem *base;
int irq;
void __iomem *mapbase;
struct clk *clk;
- struct sh_tmu_channel channel;
+ enum sh_tmu_model model;
+
+ struct sh_tmu_channel *channels;
+ unsigned int num_channels;
+
+ bool has_clockevent;
+ bool has_clocksource;
};
static DEFINE_RAW_SPINLOCK(sh_tmu_lock);
#define TCNT 1 /* channel register */
#define TCR 2 /* channel register */
+#define TCR_UNF (1 << 8)
+#define TCR_UNIE (1 << 5)
+#define TCR_TPSC_CLK4 (0 << 0)
+#define TCR_TPSC_CLK16 (1 << 0)
+#define TCR_TPSC_CLK64 (2 << 0)
+#define TCR_TPSC_CLK256 (3 << 0)
+#define TCR_TPSC_CLK1024 (4 << 0)
+#define TCR_TPSC_MASK (7 << 0)
+
static inline unsigned long sh_tmu_read(struct sh_tmu_channel *ch, int reg_nr)
{
unsigned long offs;
- if (reg_nr == TSTR)
- return ioread8(ch->tmu->mapbase);
+ if (reg_nr == TSTR) {
+ switch (ch->tmu->model) {
+ case SH_TMU_LEGACY:
+ return ioread8(ch->tmu->mapbase);
+ case SH_TMU_SH3:
+ return ioread8(ch->tmu->mapbase + 2);
+ case SH_TMU:
+ return ioread8(ch->tmu->mapbase + 4);
+ }
+ }
offs = reg_nr << 2;
unsigned long offs;
if (reg_nr == TSTR) {
- iowrite8(value, ch->tmu->mapbase);
- return;
+ switch (ch->tmu->model) {
+ case SH_TMU_LEGACY:
+ return iowrite8(value, ch->tmu->mapbase);
+ case SH_TMU_SH3:
+ return iowrite8(value, ch->tmu->mapbase + 2);
+ case SH_TMU:
+ return iowrite8(value, ch->tmu->mapbase + 4);
+ }
}
offs = reg_nr << 2;
static void sh_tmu_start_stop_ch(struct sh_tmu_channel *ch, int start)
{
- struct sh_timer_config *cfg = ch->tmu->pdev->dev.platform_data;
unsigned long flags, value;
/* start stop register shared by multiple timer channels */
value = sh_tmu_read(ch, TSTR);
if (start)
- value |= 1 << cfg->timer_bit;
+ value |= 1 << ch->index;
else
- value &= ~(1 << cfg->timer_bit);
+ value &= ~(1 << ch->index);
sh_tmu_write(ch, TSTR, value);
raw_spin_unlock_irqrestore(&sh_tmu_lock, flags);
/* enable clock */
ret = clk_enable(ch->tmu->clk);
if (ret) {
- dev_err(&ch->tmu->pdev->dev, "cannot enable clock\n");
+ dev_err(&ch->tmu->pdev->dev, "ch%u: cannot enable clock\n",
+ ch->index);
return ret;
}
/* configure channel to parent clock / 4, irq off */
ch->rate = clk_get_rate(ch->tmu->clk) / 4;
- sh_tmu_write(ch, TCR, 0x0000);
+ sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
/* enable channel */
sh_tmu_start_stop_ch(ch, 1);
sh_tmu_start_stop_ch(ch, 0);
/* disable interrupts in TMU block */
- sh_tmu_write(ch, TCR, 0x0000);
+ sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
/* stop clock */
clk_disable(ch->tmu->clk);
sh_tmu_read(ch, TCR);
/* enable interrupt */
- sh_tmu_write(ch, TCR, 0x0020);
+ sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4);
/* reload delta value in case of periodic timer */
if (periodic)
/* disable or acknowledge interrupt */
if (ch->ced.mode == CLOCK_EVT_MODE_ONESHOT)
- sh_tmu_write(ch, TCR, 0x0000);
+ sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
else
- sh_tmu_write(ch, TCR, 0x0020);
+ sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4);
/* notify clockevent layer */
ch->ced.event_handler(&ch->ced);
}
static int sh_tmu_register_clocksource(struct sh_tmu_channel *ch,
- const char *name, unsigned long rating)
+ const char *name)
{
struct clocksource *cs = &ch->cs;
cs->name = name;
- cs->rating = rating;
+ cs->rating = 200;
cs->read = sh_tmu_clocksource_read;
cs->enable = sh_tmu_clocksource_enable;
cs->disable = sh_tmu_clocksource_disable;
cs->mask = CLOCKSOURCE_MASK(32);
cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
- dev_info(&ch->tmu->pdev->dev, "used as clock source\n");
+ dev_info(&ch->tmu->pdev->dev, "ch%u: used as clock source\n",
+ ch->index);
/* Register with dummy 1 Hz value, gets updated in ->enable() */
clocksource_register_hz(cs, 1);
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
dev_info(&ch->tmu->pdev->dev,
- "used for periodic clock events\n");
+ "ch%u: used for periodic clock events\n", ch->index);
sh_tmu_clock_event_start(ch, 1);
break;
case CLOCK_EVT_MODE_ONESHOT:
dev_info(&ch->tmu->pdev->dev,
- "used for oneshot clock events\n");
+ "ch%u: used for oneshot clock events\n", ch->index);
sh_tmu_clock_event_start(ch, 0);
break;
case CLOCK_EVT_MODE_UNUSED:
}
static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch,
- const char *name, unsigned long rating)
+ const char *name)
{
struct clock_event_device *ced = &ch->ced;
int ret;
- memset(ced, 0, sizeof(*ced));
-
ced->name = name;
ced->features = CLOCK_EVT_FEAT_PERIODIC;
ced->features |= CLOCK_EVT_FEAT_ONESHOT;
- ced->rating = rating;
+ ced->rating = 200;
ced->cpumask = cpumask_of(0);
ced->set_next_event = sh_tmu_clock_event_next;
ced->set_mode = sh_tmu_clock_event_mode;
ced->suspend = sh_tmu_clock_event_suspend;
ced->resume = sh_tmu_clock_event_resume;
- dev_info(&ch->tmu->pdev->dev, "used for clock events\n");
+ dev_info(&ch->tmu->pdev->dev, "ch%u: used for clock events\n",
+ ch->index);
clockevents_config_and_register(ced, 1, 0x300, 0xffffffff);
IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
dev_name(&ch->tmu->pdev->dev), ch);
if (ret) {
- dev_err(&ch->tmu->pdev->dev, "failed to request irq %d\n",
- ch->irq);
+ dev_err(&ch->tmu->pdev->dev, "ch%u: failed to request irq %d\n",
+ ch->index, ch->irq);
return;
}
}
static int sh_tmu_register(struct sh_tmu_channel *ch, const char *name,
- unsigned long clockevent_rating,
- unsigned long clocksource_rating)
+ bool clockevent, bool clocksource)
{
- if (clockevent_rating)
- sh_tmu_register_clockevent(ch, name, clockevent_rating);
- else if (clocksource_rating)
- sh_tmu_register_clocksource(ch, name, clocksource_rating);
+ if (clockevent) {
+ ch->tmu->has_clockevent = true;
+ sh_tmu_register_clockevent(ch, name);
+ } else if (clocksource) {
+ ch->tmu->has_clocksource = true;
+ sh_tmu_register_clocksource(ch, name);
+ }
return 0;
}
-static int sh_tmu_channel_setup(struct sh_tmu_channel *ch,
+static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, unsigned int index,
+ bool clockevent, bool clocksource,
struct sh_tmu_device *tmu)
{
- struct sh_timer_config *cfg = tmu->pdev->dev.platform_data;
+ /* Skip unused channels. */
+ if (!clockevent && !clocksource)
+ return 0;
- memset(ch, 0, sizeof(*ch));
ch->tmu = tmu;
- ch->irq = platform_get_irq(tmu->pdev, 0);
+ if (tmu->model == SH_TMU_LEGACY) {
+ struct sh_timer_config *cfg = tmu->pdev->dev.platform_data;
+
+ /*
+ * The SH3 variant (SH770x, SH7705, SH7710 and SH7720) maps
+ * channel registers blocks at base + 2 + 12 * index, while all
+ * other variants map them at base + 4 + 12 * index. We can
+ * compute the index by just dividing by 12, the 2 bytes or 4
+ * bytes offset being hidden by the integer division.
+ */
+ ch->index = cfg->channel_offset / 12;
+ ch->base = tmu->mapbase + cfg->channel_offset;
+ } else {
+ ch->index = index;
+
+ if (tmu->model == SH_TMU_SH3)
+ ch->base = tmu->mapbase + 4 + ch->index * 12;
+ else
+ ch->base = tmu->mapbase + 8 + ch->index * 12;
+ }
+
+ ch->irq = platform_get_irq(tmu->pdev, ch->index);
if (ch->irq < 0) {
- dev_err(&tmu->pdev->dev, "failed to get irq\n");
+ dev_err(&tmu->pdev->dev, "ch%u: failed to get irq\n",
+ ch->index);
return ch->irq;
}
ch->enable_count = 0;
return sh_tmu_register(ch, dev_name(&tmu->pdev->dev),
- cfg->clockevent_rating,
- cfg->clocksource_rating);
+ clockevent, clocksource);
}
-static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)
+static int sh_tmu_map_memory(struct sh_tmu_device *tmu)
{
- struct sh_timer_config *cfg = pdev->dev.platform_data;
struct resource *res;
- int ret;
- ret = -ENXIO;
-
- memset(tmu, 0, sizeof(*tmu));
- tmu->pdev = pdev;
-
- if (!cfg) {
- dev_err(&tmu->pdev->dev, "missing platform data\n");
- goto err0;
- }
-
- platform_set_drvdata(pdev, tmu);
res = platform_get_resource(tmu->pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&tmu->pdev->dev, "failed to get I/O memory\n");
- goto err0;
+ return -ENXIO;
}
+ tmu->mapbase = ioremap_nocache(res->start, resource_size(res));
+ if (tmu->mapbase == NULL)
+ return -ENXIO;
+
/*
- * Map memory, let channel.base point to our channel and mapbase to the
- * start/stop shared register.
+ * In legacy platform device configuration (with one device per channel)
+ * the resource points to the channel base address.
*/
- tmu->channel.base = ioremap_nocache(res->start, resource_size(res));
- if (tmu->channel.base == NULL) {
- dev_err(&tmu->pdev->dev, "failed to remap I/O memory\n");
- goto err0;
+ if (tmu->model == SH_TMU_LEGACY) {
+ struct sh_timer_config *cfg = tmu->pdev->dev.platform_data;
+ tmu->mapbase -= cfg->channel_offset;
}
- tmu->mapbase = tmu->channel.base - cfg->channel_offset;
+ return 0;
+}
- /* get hold of clock */
- tmu->clk = clk_get(&tmu->pdev->dev, "tmu_fck");
+static void sh_tmu_unmap_memory(struct sh_tmu_device *tmu)
+{
+ if (tmu->model == SH_TMU_LEGACY) {
+ struct sh_timer_config *cfg = tmu->pdev->dev.platform_data;
+ tmu->mapbase += cfg->channel_offset;
+ }
+
+ iounmap(tmu->mapbase);
+}
+
+static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)
+{
+ struct sh_timer_config *cfg = pdev->dev.platform_data;
+ const struct platform_device_id *id = pdev->id_entry;
+ unsigned int i;
+ int ret;
+
+ if (!cfg) {
+ dev_err(&tmu->pdev->dev, "missing platform data\n");
+ return -ENXIO;
+ }
+
+ tmu->pdev = pdev;
+ tmu->model = id->driver_data;
+
+ /* Get hold of clock. */
+ tmu->clk = clk_get(&tmu->pdev->dev,
+ tmu->model == SH_TMU_LEGACY ? "tmu_fck" : "fck");
if (IS_ERR(tmu->clk)) {
dev_err(&tmu->pdev->dev, "cannot get clock\n");
- ret = PTR_ERR(tmu->clk);
- goto err1;
+ return PTR_ERR(tmu->clk);
}
ret = clk_prepare(tmu->clk);
if (ret < 0)
- goto err2;
+ goto err_clk_put;
- ret = sh_tmu_channel_setup(&tmu->channel, tmu);
- if (ret < 0)
- goto err3;
+ /* Map the memory resource. */
+ ret = sh_tmu_map_memory(tmu);
+ if (ret < 0) {
+ dev_err(&tmu->pdev->dev, "failed to remap I/O memory\n");
+ goto err_clk_unprepare;
+ }
+
+ /* Allocate and setup the channels. */
+ if (tmu->model == SH_TMU_LEGACY)
+ tmu->num_channels = 1;
+ else
+ tmu->num_channels = hweight8(cfg->channels_mask);
+
+ tmu->channels = kzalloc(sizeof(*tmu->channels) * tmu->num_channels,
+ GFP_KERNEL);
+ if (tmu->channels == NULL) {
+ ret = -ENOMEM;
+ goto err_unmap;
+ }
+
+ if (tmu->model == SH_TMU_LEGACY) {
+ ret = sh_tmu_channel_setup(&tmu->channels[0], 0,
+ cfg->clockevent_rating != 0,
+ cfg->clocksource_rating != 0, tmu);
+ if (ret < 0)
+ goto err_unmap;
+ } else {
+ /*
+ * Use the first channel as a clock event device and the second
+ * channel as a clock source.
+ */
+ for (i = 0; i < tmu->num_channels; ++i) {
+ ret = sh_tmu_channel_setup(&tmu->channels[i], i,
+ i == 0, i == 1, tmu);
+ if (ret < 0)
+ goto err_unmap;
+ }
+ }
+
+ platform_set_drvdata(pdev, tmu);
return 0;
- err3:
+err_unmap:
+ kfree(tmu->channels);
+ sh_tmu_unmap_memory(tmu);
+err_clk_unprepare:
clk_unprepare(tmu->clk);
- err2:
+err_clk_put:
clk_put(tmu->clk);
- err1:
- iounmap(tmu->channel.base);
- err0:
return ret;
}
static int sh_tmu_probe(struct platform_device *pdev)
{
struct sh_tmu_device *tmu = platform_get_drvdata(pdev);
- struct sh_timer_config *cfg = pdev->dev.platform_data;
int ret;
if (!is_early_platform_device(pdev)) {
goto out;
}
- tmu = kmalloc(sizeof(*tmu), GFP_KERNEL);
+ tmu = kzalloc(sizeof(*tmu), GFP_KERNEL);
if (tmu == NULL) {
dev_err(&pdev->dev, "failed to allocate driver data\n");
return -ENOMEM;
return 0;
out:
- if (cfg->clockevent_rating || cfg->clocksource_rating)
+ if (tmu->has_clockevent || tmu->has_clocksource)
pm_runtime_irq_safe(&pdev->dev);
else
pm_runtime_idle(&pdev->dev);
return -EBUSY; /* cannot unregister clockevent and clocksource */
}
+static const struct platform_device_id sh_tmu_id_table[] = {
+ { "sh_tmu", SH_TMU_LEGACY },
+ { "sh-tmu", SH_TMU },
+ { "sh-tmu-sh3", SH_TMU_SH3 },
+ { }
+};
+MODULE_DEVICE_TABLE(platform, sh_tmu_id_table);
+
static struct platform_driver sh_tmu_device_driver = {
.probe = sh_tmu_probe,
.remove = sh_tmu_remove,
.driver = {
.name = "sh_tmu",
- }
+ },
+ .id_table = sh_tmu_id_table,
};
static int __init sh_tmu_init(void)
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