unsigned num_region;
unsigned num_slots;
unsigned num_tc;
+ bool chmap_exist;
enum dma_event_q default_queue;
bool unused_chan_list_done;
- /* The edma_inuse bit for each PaRAM slot is clear unless the
+ /* The slot_inuse bit for each PaRAM slot is clear unless the
* channel is in use ... by ARM or DSP, for QDMA, or whatever.
*/
- unsigned long *edma_inuse;
+ unsigned long *slot_inuse;
- /* The edma_unused bit for each channel is clear unless
+ /* The channel_unused bit for each channel is clear unless
* it is not being used on this platform. It uses a bit
* of SOC-specific initialization code.
*/
- unsigned long *edma_unused;
+ unsigned long *channel_unused;
struct dma_device dma_slave;
struct edma_chan *slave_chans;
edma_modify(ecc, EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit));
}
-static void edma_direct_dmach_to_param_mapping(struct edma_cc *ecc)
+static void edma_set_chmap(struct edma_cc *ecc, int channel, int slot)
{
- int i;
-
- for (i = 0; i < ecc->num_channels; i++)
- edma_write_array(ecc, EDMA_DCHMAP, i, (i << 5));
+ if (ecc->chmap_exist) {
+ channel = EDMA_CHAN_SLOT(channel);
+ slot = EDMA_CHAN_SLOT(slot);
+ edma_write_array(ecc, EDMA_DCHMAP, channel, (slot << 5));
+ }
}
static int prepare_unused_channel_list(struct device *dev, void *data)
continue;
clear_bit(EDMA_CHAN_SLOT(dma_spec.args[0]),
- ecc->edma_unused);
+ ecc->channel_unused);
of_node_put(dma_spec.np);
}
return 0;
dma_req = (int)res->start;
if (dma_req >= dma_req_min && dma_req < dma_req_max)
clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start),
- ecc->edma_unused);
+ ecc->channel_unused);
}
return 0;
*/
static int edma_alloc_slot(struct edma_cc *ecc, int slot)
{
- if (slot > 0)
+ if (slot > 0) {
slot = EDMA_CHAN_SLOT(slot);
+ /* Requesting entry paRAM slot for a HW triggered channel. */
+ if (ecc->chmap_exist && slot < ecc->num_channels)
+ slot = EDMA_SLOT_ANY;
+ }
+
if (slot < 0) {
- slot = ecc->num_channels;
+ if (ecc->chmap_exist)
+ slot = 0;
+ else
+ slot = ecc->num_channels;
for (;;) {
- slot = find_next_zero_bit(ecc->edma_inuse,
+ slot = find_next_zero_bit(ecc->slot_inuse,
ecc->num_slots,
slot);
if (slot == ecc->num_slots)
return -ENOMEM;
- if (!test_and_set_bit(slot, ecc->edma_inuse))
+ if (!test_and_set_bit(slot, ecc->slot_inuse))
break;
}
- } else if (slot < ecc->num_channels || slot >= ecc->num_slots) {
+ } else if (slot >= ecc->num_slots) {
return -EINVAL;
- } else if (test_and_set_bit(slot, ecc->edma_inuse)) {
+ } else if (test_and_set_bit(slot, ecc->slot_inuse)) {
return -EBUSY;
}
static void edma_free_slot(struct edma_cc *ecc, unsigned slot)
{
slot = EDMA_CHAN_SLOT(slot);
- if (slot < ecc->num_channels || slot >= ecc->num_slots)
+ if (slot >= ecc->num_slots)
return;
edma_write_slot(ecc, slot, &dummy_paramset);
- clear_bit(slot, ecc->edma_inuse);
+ clear_bit(slot, ecc->slot_inuse);
}
/**
unsigned int mask = BIT(channel & 0x1f);
/* EDMA channels without event association */
- if (test_bit(channel, ecc->edma_unused)) {
+ if (test_bit(channel, ecc->channel_unused)) {
dev_dbg(ecc->dev, "ESR%d %08x\n", j,
edma_shadow0_read_array(ecc, SH_ESR, j));
edma_shadow0_write_array(ecc, SH_ESR, j, mask);
static int edma_alloc_channel(struct edma_cc *ecc, int channel,
enum dma_event_q eventq_no)
{
- unsigned done = 0;
int ret = 0;
if (!ecc->unused_chan_list_done) {
}
if (channel < 0) {
- channel = 0;
- for (;;) {
- channel = find_next_bit(ecc->edma_unused,
- ecc->num_channels, channel);
- if (channel == ecc->num_channels)
- break;
- if (!test_and_set_bit(channel, ecc->edma_inuse)) {
- done = 1;
- break;
- }
- channel++;
- }
- if (!done)
- return -ENOMEM;
+ channel = find_next_bit(ecc->channel_unused, ecc->num_channels,
+ 0);
+ if (channel == ecc->num_channels)
+ return -EBUSY;
} else if (channel >= ecc->num_channels) {
return -EINVAL;
- } else if (test_and_set_bit(channel, ecc->edma_inuse)) {
- return -EBUSY;
}
/* ensure access through shadow region 0 */
/* ensure no events are pending */
edma_stop(ecc, EDMA_CTLR_CHAN(ecc->id, channel));
- edma_write_slot(ecc, channel, &dummy_paramset);
edma_setup_interrupt(ecc, EDMA_CTLR_CHAN(ecc->id, channel), true);
if (channel >= ecc->num_channels)
return;
- edma_setup_interrupt(ecc, channel, false);
/* REVISIT should probably take out of shadow region 0 */
-
- edma_write_slot(ecc, channel, &dummy_paramset);
- clear_bit(channel, ecc->edma_inuse);
+ edma_setup_interrupt(ecc, channel, false);
}
/* Move channel to a specific event queue */
struct edma_desc *edesc;
struct device *dev = chan->device->dev;
struct edma_chan *echan = to_edma_chan(chan);
+ unsigned int width;
if (unlikely(!echan || !len))
return NULL;
edesc->pset_nr = 1;
+ width = 1 << __ffs((src | dest | len));
+ if (width > DMA_SLAVE_BUSWIDTH_64_BYTES)
+ width = DMA_SLAVE_BUSWIDTH_64_BYTES;
+
ret = edma_config_pset(chan, &edesc->pset[0], src, dest, 1,
- DMA_SLAVE_BUSWIDTH_4_BYTES, len, DMA_MEM_TO_MEM);
+ width, len, DMA_MEM_TO_MEM);
if (ret < 0)
return NULL;
spin_unlock(&echan->vchan.lock);
}
+static inline bool edma_error_pending(struct edma_cc *ecc)
+{
+ if (edma_read_array(ecc, EDMA_EMR, 0) ||
+ edma_read_array(ecc, EDMA_EMR, 1) ||
+ edma_read(ecc, EDMA_QEMR) || edma_read(ecc, EDMA_CCERR))
+ return true;
+
+ return false;
+}
+
/* eDMA error interrupt handler */
static irqreturn_t dma_ccerr_handler(int irq, void *data)
{
struct edma_cc *ecc = data;
- int i;
+ int i, j;
int ctlr;
unsigned int cnt = 0;
+ unsigned int val;
ctlr = ecc->id;
if (ctlr < 0)
dev_vdbg(ecc->dev, "dma_ccerr_handler\n");
- if ((edma_read_array(ecc, EDMA_EMR, 0) == 0) &&
- (edma_read_array(ecc, EDMA_EMR, 1) == 0) &&
- (edma_read(ecc, EDMA_QEMR) == 0) &&
- (edma_read(ecc, EDMA_CCERR) == 0))
+ if (!edma_error_pending(ecc))
return IRQ_NONE;
while (1) {
- int j = -1;
-
- if (edma_read_array(ecc, EDMA_EMR, 0))
- j = 0;
- else if (edma_read_array(ecc, EDMA_EMR, 1))
- j = 1;
- if (j >= 0) {
- dev_dbg(ecc->dev, "EMR%d %08x\n", j,
- edma_read_array(ecc, EDMA_EMR, j));
- for (i = 0; i < 32; i++) {
+ /* Event missed register(s) */
+ for (j = 0; j < 2; j++) {
+ unsigned long emr;
+
+ val = edma_read_array(ecc, EDMA_EMR, j);
+ if (!val)
+ continue;
+
+ dev_dbg(ecc->dev, "EMR%d 0x%08x\n", j, val);
+ emr = val;
+ for (i = find_next_bit(&emr, 32, 0); i < 32;
+ i = find_next_bit(&emr, 32, i + 1)) {
int k = (j << 5) + i;
- if (edma_read_array(ecc, EDMA_EMR, j) &
- BIT(i)) {
- /* Clear the corresponding EMR bits */
- edma_write_array(ecc, EDMA_EMCR, j,
+ /* Clear the corresponding EMR bits */
+ edma_write_array(ecc, EDMA_EMCR, j, BIT(i));
+ /* Clear any SER */
+ edma_shadow0_write_array(ecc, SH_SECR, j,
BIT(i));
- /* Clear any SER */
- edma_shadow0_write_array(ecc, SH_SECR,
- j, BIT(i));
- edma_error_handler(&ecc->slave_chans[k]);
- }
- }
- } else if (edma_read(ecc, EDMA_QEMR)) {
- dev_dbg(ecc->dev, "QEMR %02x\n",
- edma_read(ecc, EDMA_QEMR));
- for (i = 0; i < 8; i++) {
- if (edma_read(ecc, EDMA_QEMR) & BIT(i)) {
- /* Clear the corresponding IPR bits */
- edma_write(ecc, EDMA_QEMCR, BIT(i));
- edma_shadow0_write(ecc, SH_QSECR,
- BIT(i));
-
- /* NOTE: not reported!! */
- }
- }
- } else if (edma_read(ecc, EDMA_CCERR)) {
- dev_dbg(ecc->dev, "CCERR %08x\n",
- edma_read(ecc, EDMA_CCERR));
- /* FIXME: CCERR.BIT(16) ignored! much better
- * to just write CCERRCLR with CCERR value...
- */
- for (i = 0; i < 8; i++) {
- if (edma_read(ecc, EDMA_CCERR) & BIT(i)) {
- /* Clear the corresponding IPR bits */
- edma_write(ecc, EDMA_CCERRCLR, BIT(i));
-
- /* NOTE: not reported!! */
- }
+ edma_error_handler(&ecc->slave_chans[k]);
}
}
- if ((edma_read_array(ecc, EDMA_EMR, 0) == 0) &&
- (edma_read_array(ecc, EDMA_EMR, 1) == 0) &&
- (edma_read(ecc, EDMA_QEMR) == 0) &&
- (edma_read(ecc, EDMA_CCERR) == 0))
+
+ val = edma_read(ecc, EDMA_QEMR);
+ if (val) {
+ dev_dbg(ecc->dev, "QEMR 0x%02x\n", val);
+ /* Not reported, just clear the interrupt reason. */
+ edma_write(ecc, EDMA_QEMCR, val);
+ edma_shadow0_write(ecc, SH_QSECR, val);
+ }
+
+ val = edma_read(ecc, EDMA_CCERR);
+ if (val) {
+ dev_warn(ecc->dev, "CCERR 0x%08x\n", val);
+ /* Not reported, just clear the interrupt reason. */
+ edma_write(ecc, EDMA_CCERRCLR, val);
+ }
+
+ if (!edma_error_pending(ecc))
break;
cnt++;
if (cnt > 10)
}
echan->alloced = true;
- echan->slot[0] = echan->ch_num;
+ echan->slot[0] = edma_alloc_slot(echan->ecc, echan->ch_num);
+ if (echan->slot[0] < 0) {
+ dev_err(dev, "Entry slot allocation failed for channel %u\n",
+ EDMA_CHAN_SLOT(echan->ch_num));
+ goto err_wrong_chan;
+ }
+
+ /* Set up channel -> slot mapping for the entry slot */
+ edma_set_chmap(echan->ecc, echan->ch_num, echan->slot[0]);
dev_dbg(dev, "allocated channel %d for %u:%u\n", echan->ch_num,
EDMA_CTLR(echan->ch_num), EDMA_CHAN_SLOT(echan->ch_num));
vchan_free_chan_resources(&echan->vchan);
/* Free EDMA PaRAM slots */
- for (i = 1; i < EDMA_MAX_SLOTS; i++) {
+ for (i = 0; i < EDMA_MAX_SLOTS; i++) {
if (echan->slot[i] >= 0) {
edma_free_slot(echan->ecc, echan->slot[i]);
echan->slot[i] = -1;
}
}
+ /* Set entry slot to the dummy slot */
+ edma_set_chmap(echan->ecc, echan->ch_num, echan->ecc->dummy_slot);
+
/* Free EDMA channel */
if (echan->alloced) {
edma_free_channel(echan->ecc, echan->ch_num);
dma->dev = dev;
- /*
- * code using dma memcpy must make sure alignment of
- * length is at dma->copy_align boundary.
- */
- dma->copy_align = DMAENGINE_ALIGN_4_BYTES;
-
INIT_LIST_HEAD(&dma->channels);
}
value = GET_NUM_EVQUE(cccfg);
ecc->num_tc = value + 1;
+ ecc->chmap_exist = (cccfg & CHMAP_EXIST) ? true : false;
+
dev_dbg(dev, "eDMA3 CC HW configuration (cccfg: 0x%08x):\n", cccfg);
dev_dbg(dev, "num_region: %u\n", ecc->num_region);
dev_dbg(dev, "num_channels: %u\n", ecc->num_channels);
dev_dbg(dev, "num_slots: %u\n", ecc->num_slots);
dev_dbg(dev, "num_tc: %u\n", ecc->num_tc);
+ dev_dbg(dev, "chmap_exist: %s\n", ecc->chmap_exist ? "yes" : "no");
/* Nothing need to be done if queue priority is provided */
if (pdata->queue_priority_mapping)
if (!ecc->slave_chans)
return -ENOMEM;
- ecc->edma_unused = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_channels),
- sizeof(unsigned long), GFP_KERNEL);
- if (!ecc->edma_unused)
+ ecc->channel_unused = devm_kcalloc(dev,
+ BITS_TO_LONGS(ecc->num_channels),
+ sizeof(unsigned long), GFP_KERNEL);
+ if (!ecc->channel_unused)
return -ENOMEM;
- ecc->edma_inuse = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_slots),
+ ecc->slot_inuse = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_slots),
sizeof(unsigned long), GFP_KERNEL);
- if (!ecc->edma_inuse)
+ if (!ecc->slot_inuse)
return -ENOMEM;
ecc->default_queue = info->default_queue;
edma_write_slot(ecc, i, &dummy_paramset);
/* Mark all channels as unused */
- memset(ecc->edma_unused, 0xff, sizeof(ecc->edma_unused));
+ memset(ecc->channel_unused, 0xff, sizeof(ecc->channel_unused));
if (info->rsv) {
/* Clear the reserved channels in unused list */
for (i = 0; rsv_chans[i][0] != -1; i++) {
off = rsv_chans[i][0];
ln = rsv_chans[i][1];
- clear_bits(off, ln, ecc->edma_unused);
+ clear_bits(off, ln, ecc->channel_unused);
}
}
for (i = 0; rsv_slots[i][0] != -1; i++) {
off = rsv_slots[i][0];
ln = rsv_slots[i][1];
- set_bits(off, ln, ecc->edma_inuse);
+ set_bits(off, ln, ecc->slot_inuse);
}
}
}
if (xbar_chans) {
for (i = 0; xbar_chans[i][1] != -1; i++) {
off = xbar_chans[i][1];
- clear_bits(off, 1, ecc->edma_unused);
+ clear_bits(off, 1, ecc->channel_unused);
}
}
}
}
- for (i = 0; i < ecc->num_channels; i++)
+ ecc->dummy_slot = edma_alloc_slot(ecc, EDMA_SLOT_ANY);
+ if (ecc->dummy_slot < 0) {
+ dev_err(dev, "Can't allocate PaRAM dummy slot\n");
+ return ecc->dummy_slot;
+ }
+
+ for (i = 0; i < ecc->num_channels; i++) {
+ /* Assign all channels to the default queue */
edma_map_dmach_to_queue(ecc, i, info->default_queue);
+ /* Set entry slot to the dummy slot */
+ edma_set_chmap(ecc, i, ecc->dummy_slot);
+ }
queue_priority_mapping = info->queue_priority_mapping;
edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0],
queue_priority_mapping[i][1]);
- /* Map the channel to param entry if channel mapping logic exist */
- if (edma_read(ecc, EDMA_CCCFG) & CHMAP_EXIST)
- edma_direct_dmach_to_param_mapping(ecc);
-
for (i = 0; i < ecc->num_region; i++) {
edma_write_array2(ecc, EDMA_DRAE, i, 0, 0x0);
edma_write_array2(ecc, EDMA_DRAE, i, 1, 0x0);
}
ecc->info = info;
- ecc->dummy_slot = edma_alloc_slot(ecc, EDMA_SLOT_ANY);
- if (ecc->dummy_slot < 0) {
- dev_err(dev, "Can't allocate PaRAM dummy slot\n");
- return ecc->dummy_slot;
- }
-
dma_cap_zero(ecc->dma_slave.cap_mask);
dma_cap_set(DMA_SLAVE, ecc->dma_slave.cap_mask);
dma_cap_set(DMA_CYCLIC, ecc->dma_slave.cap_mask);
static int edma_pm_resume(struct device *dev)
{
struct edma_cc *ecc = dev_get_drvdata(dev);
+ struct edma_chan *echan = ecc->slave_chans;
int i;
s8 (*queue_priority_mapping)[2];
edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0],
queue_priority_mapping[i][1]);
- /* Map the channel to param entry if channel mapping logic */
- if (edma_read(ecc, EDMA_CCCFG) & CHMAP_EXIST)
- edma_direct_dmach_to_param_mapping(ecc);
-
for (i = 0; i < ecc->num_channels; i++) {
- if (test_bit(i, ecc->edma_inuse)) {
+ if (echan[i].alloced) {
/* ensure access through shadow region 0 */
edma_or_array2(ecc, EDMA_DRAE, 0, i >> 5,
BIT(i & 0x1f));
edma_setup_interrupt(ecc, EDMA_CTLR_CHAN(ecc->id, i),
true);
+
+ /* Set up channel -> slot mapping for the entry slot */
+ edma_set_chmap(ecc, echan[i].ch_num, echan[i].slot[0]);
}
}
projects / deliverable / linux.git / blobdiff