Merge branch 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jack/linux...

[deliverable/linux.git] / drivers / edac / edac_mce_amd.c

diff --git a/drivers/edac/edac_mce_amd.c b/drivers/edac/edac_mce_amd.c
index fe8ccebd9672489a936293519b6ed22a80865f26..0c21c370c9dd001c2da04e1c914c5248708f219e 100644 (file)
--- a/drivers/edac/edac_mce_amd.c
+++ b/drivers/edac/edac_mce_amd.c
@@ -171,6 +171,126 @@ wrong_dc_mce:
        pr_warning("Corrupted DC MCE info?\n");
 }
 
+static void amd_decode_ic_mce(u64 mc1_status)
+{
+       u32 ec  = mc1_status & 0xffff;
+       u32 xec = (mc1_status >> 16) & 0xf;
+
+       pr_emerg(" Instruction Cache Error");
+
+       if (xec == 1 && TLB_ERROR(ec))
+               pr_cont(": %s TLB multimatch.\n", LL_MSG(ec));
+       else if (xec == 0) {
+               if (TLB_ERROR(ec))
+                       pr_cont(": %s TLB Parity error.\n", LL_MSG(ec));
+               else if (BUS_ERROR(ec)) {
+                       if (boot_cpu_data.x86 == 0xf &&
+                           (mc1_status & (1ULL << 58)))
+                               pr_cont(" during system linefill.\n");
+                       else
+                               pr_cont(" during attempted NB data read.\n");
+               } else if (MEM_ERROR(ec)) {
+                       u8 ll   = ec & 0x3;
+                       u8 rrrr = (ec >> 4) & 0xf;
+
+                       if (ll == 0x2)
+                               pr_cont(" during a linefill from L2.\n");
+                       else if (ll == 0x1) {
+
+                               switch (rrrr) {
+                               case 0x5:
+                                       pr_cont(": Parity error during "
+                                              "data load.\n");
+                                       break;
+
+                               case 0x7:
+                                       pr_cont(": Copyback Parity/Victim"
+                                               " error.\n");
+                                       break;
+
+                               case 0x8:
+                                       pr_cont(": Tag Snoop error.\n");
+                                       break;
+
+                               default:
+                                       goto wrong_ic_mce;
+                                       break;
+                               }
+                       }
+               } else
+                       goto wrong_ic_mce;
+       } else
+               goto wrong_ic_mce;
+
+       return;
+
+wrong_ic_mce:
+       pr_warning("Corrupted IC MCE info?\n");
+}
+
+static void amd_decode_bu_mce(u64 mc2_status)
+{
+       u32 ec = mc2_status & 0xffff;
+       u32 xec = (mc2_status >> 16) & 0xf;
+
+       pr_emerg(" Bus Unit Error");
+
+       if (xec == 0x1)
+               pr_cont(" in the write data buffers.\n");
+       else if (xec == 0x3)
+               pr_cont(" in the victim data buffers.\n");
+       else if (xec == 0x2 && MEM_ERROR(ec))
+               pr_cont(": %s error in the L2 cache tags.\n", RRRR_MSG(ec));
+       else if (xec == 0x0) {
+               if (TLB_ERROR(ec))
+                       pr_cont(": %s error in a Page Descriptor Cache or "
+                               "Guest TLB.\n", TT_MSG(ec));
+               else if (BUS_ERROR(ec))
+                       pr_cont(": %s/ECC error in data read from NB: %s.\n",
+                               RRRR_MSG(ec), PP_MSG(ec));
+               else if (MEM_ERROR(ec)) {
+                       u8 rrrr = (ec >> 4) & 0xf;
+
+                       if (rrrr >= 0x7)
+                               pr_cont(": %s error during data copyback.\n",
+                                       RRRR_MSG(ec));
+                       else if (rrrr <= 0x1)
+                               pr_cont(": %s parity/ECC error during data "
+                                       "access from L2.\n", RRRR_MSG(ec));
+                       else
+                               goto wrong_bu_mce;
+               } else
+                       goto wrong_bu_mce;
+       } else
+               goto wrong_bu_mce;
+
+       return;
+
+wrong_bu_mce:
+       pr_warning("Corrupted BU MCE info?\n");
+}
+
+static void amd_decode_ls_mce(u64 mc3_status)
+{
+       u32 ec  = mc3_status & 0xffff;
+       u32 xec = (mc3_status >> 16) & 0xf;
+
+       pr_emerg(" Load Store Error");
+
+       if (xec == 0x0) {
+               u8 rrrr = (ec >> 4) & 0xf;
+
+               if (!BUS_ERROR(ec) || (rrrr != 0x3 && rrrr != 0x4))
+                       goto wrong_ls_mce;
+
+               pr_cont(" during %s.\n", RRRR_MSG(ec));
+       }
+       return;
+
+wrong_ls_mce:
+       pr_warning("Corrupted LS MCE info?\n");
+}
+
 void amd_decode_nb_mce(int node_id, struct err_regs *regs, int handle_errors)
 {
        u32 ec  = ERROR_CODE(regs->nbsl);
@@ -201,6 +321,15 @@ void amd_decode_nb_mce(int node_id, struct err_regs *regs, int handle_errors)
 }
 EXPORT_SYMBOL_GPL(amd_decode_nb_mce);
 
+static void amd_decode_fr_mce(u64 mc5_status)
+{
+       /* we have only one error signature so match all fields at once. */
+       if ((mc5_status & 0xffff) == 0x0f0f)
+               pr_emerg(" FR Error: CPU Watchdog timer expire.\n");
+       else
+               pr_warning("Corrupted FR MCE info?\n");
+}
+
 static inline void amd_decode_err_code(unsigned int ec)
 {
        if (TLB_ERROR(ec)) {
@@ -259,16 +388,32 @@ void decode_mce(struct mce *m)
                amd_decode_dc_mce(m->status);
                break;
 
+       case 1:
+               amd_decode_ic_mce(m->status);
+               break;
+
+       case 2:
+               amd_decode_bu_mce(m->status);
+               break;
+
+       case 3:
+               amd_decode_ls_mce(m->status);
+               break;
+
        case 4:
                regs.nbsl  = (u32) m->status;
                regs.nbsh  = (u32)(m->status >> 32);
                regs.nbeal = (u32) m->addr;
                regs.nbeah = (u32)(m->addr >> 32);
-               node       = per_cpu(cpu_llc_id, m->extcpu);
+               node       = amd_get_nb_id(m->extcpu);
 
                amd_decode_nb_mce(node, &regs, 1);
                break;
 
+       case 5:
+               amd_decode_fr_mce(m->status);
+               break;
+
        default:
                break;
        }