drm/amdgpu: merge amdgpu_family.h into amd_shared.h (v2)

[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / cik.c

diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index b3b66a0d5ff7ce2d6f3fa36ae7b2cdb25cb468b8..4b6ce74753cded5179b17eaf698ddd16766760b1 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -838,7 +838,7 @@ static u32 cik_get_xclk(struct amdgpu_device *adev)
 {
        u32 reference_clock = adev->clock.spll.reference_freq;
 
-       if (adev->flags & AMDGPU_IS_APU) {
+       if (adev->flags & AMD_IS_APU) {
                if (RREG32_SMC(ixGENERAL_PWRMGT) & GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK)
                        return reference_clock / 2;
        } else {
@@ -1235,7 +1235,7 @@ static void cik_gpu_soft_reset(struct amdgpu_device *adev, u32 reset_mask)
        if (reset_mask & AMDGPU_RESET_VMC)
                srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_VMC_MASK;
 
-       if (!(adev->flags & AMDGPU_IS_APU)) {
+       if (!(adev->flags & AMD_IS_APU)) {
                if (reset_mask & AMDGPU_RESET_MC)
                        srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_MC_MASK;
        }
@@ -1411,7 +1411,7 @@ static void cik_gpu_pci_config_reset(struct amdgpu_device *adev)
                dev_warn(adev->dev, "Wait for MC idle timed out !\n");
        }
 
-       if (adev->flags & AMDGPU_IS_APU)
+       if (adev->flags & AMD_IS_APU)
                kv_save_regs_for_reset(adev, &kv_save);
 
        /* disable BM */
@@ -1429,7 +1429,7 @@ static void cik_gpu_pci_config_reset(struct amdgpu_device *adev)
        }
 
        /* does asic init need to be run first??? */
-       if (adev->flags & AMDGPU_IS_APU)
+       if (adev->flags & AMD_IS_APU)
                kv_restore_regs_for_reset(adev, &kv_save);
 }
 
@@ -1570,7 +1570,7 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
        if (amdgpu_pcie_gen2 == 0)
                return;
 
-       if (adev->flags & AMDGPU_IS_APU)
+       if (adev->flags & AMD_IS_APU)
                return;
 
        ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
@@ -1730,7 +1730,7 @@ static void cik_program_aspm(struct amdgpu_device *adev)
                return;
 
        /* XXX double check APUs */
-       if (adev->flags & AMDGPU_IS_APU)
+       if (adev->flags & AMD_IS_APU)
                return;
 
        orig = data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL);