drm/amdgpu: rename amdgpu_ip_funcs to amd_ip_funcs (v2)

[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / uvd_v5_0.c

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index f3b3026d59325e8bf2bad569cfd02c644fe87f4f..004c56496fc473cb5c2aebbeef4c3b27df4ce5e6 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -79,17 +79,20 @@ static void uvd_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
        WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
 }
 
-static int uvd_v5_0_early_init(struct amdgpu_device *adev)
+static int uvd_v5_0_early_init(void *handle)
 {
+       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
        uvd_v5_0_set_ring_funcs(adev);
        uvd_v5_0_set_irq_funcs(adev);
 
        return 0;
 }
 
-static int uvd_v5_0_sw_init(struct amdgpu_device *adev)
+static int uvd_v5_0_sw_init(void *handle)
 {
        struct amdgpu_ring *ring;
+       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
        int r;
 
        /* UVD TRAP */
@@ -113,9 +116,10 @@ static int uvd_v5_0_sw_init(struct amdgpu_device *adev)
        return r;
 }
 
-static int uvd_v5_0_sw_fini(struct amdgpu_device *adev)
+static int uvd_v5_0_sw_fini(void *handle)
 {
        int r;
+       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
        r = amdgpu_uvd_suspend(adev);
        if (r)
@@ -135,8 +139,9 @@ static int uvd_v5_0_sw_fini(struct amdgpu_device *adev)
  *
  * Initialize the hardware, boot up the VCPU and do some testing
  */
-static int uvd_v5_0_hw_init(struct amdgpu_device *adev)
+static int uvd_v5_0_hw_init(void *handle)
 {
+       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
        struct amdgpu_ring *ring = &adev->uvd.ring;
        uint32_t tmp;
        int r;
@@ -199,8 +204,9 @@ done:
  *
  * Stop the UVD block, mark ring as not ready any more
  */
-static int uvd_v5_0_hw_fini(struct amdgpu_device *adev)
+static int uvd_v5_0_hw_fini(void *handle)
 {
+       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
        struct amdgpu_ring *ring = &adev->uvd.ring;
 
        uvd_v5_0_stop(adev);
@@ -209,9 +215,10 @@ static int uvd_v5_0_hw_fini(struct amdgpu_device *adev)
        return 0;
 }
 
-static int uvd_v5_0_suspend(struct amdgpu_device *adev)
+static int uvd_v5_0_suspend(void *handle)
 {
        int r;
+       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
        r = uvd_v5_0_hw_fini(adev);
        if (r)
@@ -224,9 +231,10 @@ static int uvd_v5_0_suspend(struct amdgpu_device *adev)
        return r;
 }
 
-static int uvd_v5_0_resume(struct amdgpu_device *adev)
+static int uvd_v5_0_resume(void *handle)
 {
        int r;
+       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
        r = amdgpu_uvd_resume(adev);
        if (r)
@@ -605,14 +613,17 @@ error:
        return r;
 }
 
-static bool uvd_v5_0_is_idle(struct amdgpu_device *adev)
+static bool uvd_v5_0_is_idle(void *handle)
 {
+       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
        return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
 }
 
-static int uvd_v5_0_wait_for_idle(struct amdgpu_device *adev)
+static int uvd_v5_0_wait_for_idle(void *handle)
 {
        unsigned i;
+       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
        for (i = 0; i < adev->usec_timeout; i++) {
                if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))
@@ -621,8 +632,10 @@ static int uvd_v5_0_wait_for_idle(struct amdgpu_device *adev)
        return -ETIMEDOUT;
 }
 
-static int uvd_v5_0_soft_reset(struct amdgpu_device *adev)
+static int uvd_v5_0_soft_reset(void *handle)
 {
+       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
        uvd_v5_0_stop(adev);
 
        WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,
@@ -632,8 +645,9 @@ static int uvd_v5_0_soft_reset(struct amdgpu_device *adev)
        return uvd_v5_0_start(adev);
 }
 
-static void uvd_v5_0_print_status(struct amdgpu_device *adev)
+static void uvd_v5_0_print_status(void *handle)
 {
+       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
        dev_info(adev->dev, "UVD 5.0 registers\n");
        dev_info(adev->dev, "  UVD_SEMA_ADDR_LOW=0x%08X\n",
                 RREG32(mmUVD_SEMA_ADDR_LOW));
@@ -757,16 +771,14 @@ static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev,
        return 0;
 }
 
-static int uvd_v5_0_set_clockgating_state(struct amdgpu_device *adev,
-                                         enum amdgpu_clockgating_state state)
+static int uvd_v5_0_set_clockgating_state(void *handle,
+                                         enum amd_clockgating_state state)
 {
-       //TODO
-
        return 0;
 }
 
-static int uvd_v5_0_set_powergating_state(struct amdgpu_device *adev,
-                                         enum amdgpu_powergating_state state)
+static int uvd_v5_0_set_powergating_state(void *handle,
+                                         enum amd_powergating_state state)
 {
        /* This doesn't actually powergate the UVD block.
         * That's done in the dpm code via the SMC.  This
@@ -775,7 +787,9 @@ static int uvd_v5_0_set_powergating_state(struct amdgpu_device *adev,
         * revisit this when there is a cleaner line between
         * the smc and the hw blocks
         */
-       if (state == AMDGPU_PG_STATE_GATE) {
+       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+       if (state == AMD_PG_STATE_GATE) {
                uvd_v5_0_stop(adev);
                return 0;
        } else {
@@ -783,7 +797,7 @@ static int uvd_v5_0_set_powergating_state(struct amdgpu_device *adev,
        }
 }
 
-const struct amdgpu_ip_funcs uvd_v5_0_ip_funcs = {
+const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
        .early_init = uvd_v5_0_early_init,
        .late_init = NULL,
        .sw_init = uvd_v5_0_sw_init,