Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net

[deliverable/linux.git] / drivers / gpu / drm / amd / include / amd_pcie.h

diff --git a/drivers/gpu/drm/amd/include/amd_pcie.h b/drivers/gpu/drm/amd/include/amd_pcie.h
index 7c2a916c1e63c3e6a00bfeafbda7a92444725085..5eb895fd98bfb6a65de4fd16e595d85c12d7830d 100644 (file)
--- a/drivers/gpu/drm/amd/include/amd_pcie.h
+++ b/drivers/gpu/drm/amd/include/amd_pcie.h
@@ -37,6 +37,13 @@
 #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK   0x0000FFFF
 #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_SHIFT  0
 
+/* gen: chipset 1/2, asic 1/2/3 */
+#define AMDGPU_DEFAULT_PCIE_GEN_MASK (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 \
+                                     | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 \
+                                     | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 \
+                                     | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 \
+                                     | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3)
+
 /* Following flags shows PCIe lane width switch supported in driver which are decided by chipset and ASIC */
 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X1          0x00010000
 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X2          0x00020000
@@ -47,4 +54,11 @@
 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X32         0x00400000
 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_SHIFT       16
 
+/* 1/2/4/8/16 lanes */
+#define AMDGPU_DEFAULT_PCIE_MLW_MASK (CAIL_PCIE_LINK_WIDTH_SUPPORT_X1 \
+                                     | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 \
+                                     | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 \
+                                     | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 \
+                                     | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
+
 #endif