drm/amd/powerplay: add CG and PG support for carrizo

[deliverable/linux.git] / drivers / gpu / drm / amd / powerplay / hwmgr / hardwaremanager.c

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
index 7317e43fe8b18a508a5aded3bd5ee4e4884b328f..aec9f6d8e47652bcb466f3c79076ede2ea8d9500 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
@@ -23,6 +23,7 @@
 #include <linux/errno.h>
 #include "hwmgr.h"
 #include "hardwaremanager.h"
+#include "power_state.h"
 #include "pp_acpi.h"
 #include "amd_acpi.h"
 
@@ -55,6 +56,17 @@ void phm_init_dynamic_caps(struct pp_hwmgr *hwmgr)
                phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
 }
 
+bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr)
+{
+       return hwmgr->block_hw_access;
+}
+
+int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block)
+{
+       hwmgr->block_hw_access = block;
+       return 0;
+}
+
 int phm_setup_asic(struct pp_hwmgr *hwmgr)
 {
        if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
@@ -62,13 +74,33 @@ int phm_setup_asic(struct pp_hwmgr *hwmgr)
                if (NULL != hwmgr->hwmgr_func->asic_setup)
                        return hwmgr->hwmgr_func->asic_setup(hwmgr);
        } else {
-               return phm_dispatch_table (hwmgr, &(hwmgr->setup_asic),
+               return phm_dispatch_table(hwmgr, &(hwmgr->setup_asic),
                                          NULL, NULL);
        }
 
        return 0;
 }
 
+int phm_set_power_state(struct pp_hwmgr *hwmgr,
+                   const struct pp_hw_power_state *pcurrent_state,
+                   const struct pp_hw_power_state *pnew_power_state)
+{
+       struct phm_set_power_state_input states;
+
+       states.pcurrent_state = pcurrent_state;
+       states.pnew_state = pnew_power_state;
+
+       if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+               PHM_PlatformCaps_TablelessHardwareInterface)) {
+               if (NULL != hwmgr->hwmgr_func->power_state_set)
+                       return hwmgr->hwmgr_func->power_state_set(hwmgr, &states);
+       } else {
+               return phm_dispatch_table(hwmgr, &(hwmgr->set_power_state), &states, NULL);
+       }
+
+       return 0;
+}
+
 int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
 {
        if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
@@ -76,9 +108,62 @@ int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
                if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
                        return hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
        } else {
-               return phm_dispatch_table (hwmgr,
+               return phm_dispatch_table(hwmgr,
                                &(hwmgr->enable_dynamic_state_management),
                                NULL, NULL);
        }
        return 0;
 }
+
+int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level)
+{
+       if (hwmgr->hwmgr_func->force_dpm_level != NULL)
+               return hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
+
+       return 0;
+}
+
+int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
+                                  struct pp_power_state *adjusted_ps,
+                            const struct pp_power_state *current_ps)
+{
+       if (hwmgr->hwmgr_func->apply_state_adjust_rules != NULL)
+               return hwmgr->hwmgr_func->apply_state_adjust_rules(
+                                                                       hwmgr,
+                                                                adjusted_ps,
+                                                                current_ps);
+       return 0;
+}
+
+int phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
+{
+       if (hwmgr->hwmgr_func->powerdown_uvd != NULL)
+               return hwmgr->hwmgr_func->powerdown_uvd(hwmgr);
+       return 0;
+}
+
+int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate)
+{
+       if (hwmgr->hwmgr_func->powergate_uvd != NULL)
+               return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
+       return 0;
+}
+
+int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate)
+{
+       if (hwmgr->hwmgr_func->powergate_vce != NULL)
+               return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
+       return 0;
+}
+
+int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr)
+{
+       if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+               PHM_PlatformCaps_TablelessHardwareInterface)) {
+               if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating)
+                       return hwmgr->hwmgr_func->enable_clock_power_gating(hwmgr);
+       } else {
+               return phm_dispatch_table(hwmgr, &(hwmgr->enable_clock_power_gatings), NULL, NULL);
+       }
+       return 0;
+}