drm/i915: Make the ring IMR handling private

[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 22821994b35a8e421c029a9794dd04bccdf71e06..7243d64186516bd6947150a218fd3478eb0e9802 100644 (file)
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -456,8 +456,14 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
        }
        seq_printf(m, "Interrupts received: %d\n",
                   atomic_read(&dev_priv->irq_received));
-       for (i = 0; i < I915_NUM_RINGS; i++)
+       for (i = 0; i < I915_NUM_RINGS; i++) {
+               if (IS_GEN6(dev)) {
+                       seq_printf(m, "Graphics Interrupt mask (%s):    %08x\n",
+                                  dev_priv->ring[i].name,
+                                  I915_READ_IMR(&dev_priv->ring[i]));
+               }
                i915_ring_seqno_info(m, &dev_priv->ring[i]);
+       }
        mutex_unlock(&dev->struct_mutex);
 
        return 0;
@@ -797,15 +803,51 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused)
        struct drm_info_node *node = (struct drm_info_node *) m->private;
        struct drm_device *dev = node->minor->dev;
        drm_i915_private_t *dev_priv = dev->dev_private;
-       u16 rgvswctl = I915_READ16(MEMSWCTL);
-       u16 rgvstat = I915_READ16(MEMSTAT_ILK);
 
-       seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
-       seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
-       seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
-                  MEMSTAT_VID_SHIFT);
-       seq_printf(m, "Current P-state: %d\n",
-                  (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
+       if (IS_GEN5(dev)) {
+               u16 rgvswctl = I915_READ16(MEMSWCTL);
+               u16 rgvstat = I915_READ16(MEMSTAT_ILK);
+
+               seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
+               seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
+               seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
+                          MEMSTAT_VID_SHIFT);
+               seq_printf(m, "Current P-state: %d\n",
+                          (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
+       } else if (IS_GEN6(dev)) {
+               u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
+               u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
+               u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
+               int max_freq;
+
+               /* RPSTAT1 is in the GT power well */
+               __gen6_force_wake_get(dev_priv);
+
+               seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
+               seq_printf(m, "RPSTAT1: 0x%08x\n", I915_READ(GEN6_RPSTAT1));
+               seq_printf(m, "Render p-state ratio: %d\n",
+                          (gt_perf_status & 0xff00) >> 8);
+               seq_printf(m, "Render p-state VID: %d\n",
+                          gt_perf_status & 0xff);
+               seq_printf(m, "Render p-state limit: %d\n",
+                          rp_state_limits & 0xff);
+
+               max_freq = (rp_state_cap & 0xff0000) >> 16;
+               seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
+                          max_freq * 100);
+
+               max_freq = (rp_state_cap & 0xff00) >> 8;
+               seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
+                          max_freq * 100);
+
+               max_freq = rp_state_cap & 0xff;
+               seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
+                          max_freq * 100);
+
+               __gen6_force_wake_put(dev_priv);
+       } else {
+               seq_printf(m, "no P-state info available\n");
+       }
 
        return 0;
 }
@@ -933,7 +975,7 @@ static int i915_sr_status(struct seq_file *m, void *unused)
        drm_i915_private_t *dev_priv = dev->dev_private;
        bool sr_enabled = false;
 
-       if (IS_GEN5(dev))
+       if (HAS_PCH_SPLIT(dev))
                sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
        else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
                sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;