drm/i915: Use hash tables for the command parser

[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_drv.h

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 272aa7a6fbdb87f7de20e2e7df1d676f49699756..5efe3222f1e8ace9d0d077f8d489626740019319 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -325,7 +325,6 @@ struct drm_i915_error_state {
        u32 gab_ctl;
        u32 gfx_mode;
        u32 extra_instdone[I915_NUM_INSTDONE_REG];
-       u32 pipestat[I915_MAX_PIPES];
        u64 fence[I915_MAX_NUM_FENCES];
        struct intel_overlay_error_state *overlay;
        struct intel_display_error_state *display;
@@ -820,6 +819,67 @@ struct i915_suspend_saved_registers {
        u32 savePCH_PORT_HOTPLUG;
 };
 
+struct vlv_s0ix_state {
+       /* GAM */
+       u32 wr_watermark;
+       u32 gfx_prio_ctrl;
+       u32 arb_mode;
+       u32 gfx_pend_tlb0;
+       u32 gfx_pend_tlb1;
+       u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
+       u32 media_max_req_count;
+       u32 gfx_max_req_count;
+       u32 render_hwsp;
+       u32 ecochk;
+       u32 bsd_hwsp;
+       u32 blt_hwsp;
+       u32 tlb_rd_addr;
+
+       /* MBC */
+       u32 g3dctl;
+       u32 gsckgctl;
+       u32 mbctl;
+
+       /* GCP */
+       u32 ucgctl1;
+       u32 ucgctl3;
+       u32 rcgctl1;
+       u32 rcgctl2;
+       u32 rstctl;
+       u32 misccpctl;
+
+       /* GPM */
+       u32 gfxpause;
+       u32 rpdeuhwtc;
+       u32 rpdeuc;
+       u32 ecobus;
+       u32 pwrdwnupctl;
+       u32 rp_down_timeout;
+       u32 rp_deucsw;
+       u32 rcubmabdtmr;
+       u32 rcedata;
+       u32 spare2gh;
+
+       /* Display 1 CZ domain */
+       u32 gt_imr;
+       u32 gt_ier;
+       u32 pm_imr;
+       u32 pm_ier;
+       u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
+
+       /* GT SA CZ domain */
+       u32 tilectl;
+       u32 gt_fifoctl;
+       u32 gtlc_wake_ctrl;
+       u32 gtlc_survive;
+       u32 pmwgicz;
+
+       /* Display 2 CZ domain */
+       u32 gu_ctl0;
+       u32 gu_ctl1;
+       u32 clock_gate_dis2;
+};
+
 struct intel_gen6_power_mgmt {
        /* work and pm_iir are protected by dev_priv->irq_lock */
        struct work_struct work;
@@ -929,6 +989,7 @@ struct i915_power_domains {
         * time are on. They are kept on until after the first modeset.
         */
        bool init_power_on;
+       bool initializing;
        int power_well_count;
 
        struct mutex lock;
@@ -1448,6 +1509,7 @@ struct drm_i915_private {
 
        u32 suspend_count;
        struct i915_suspend_saved_registers regfile;
+       struct vlv_s0ix_state vlv_s0ix_state;
 
        struct {
                /*
@@ -1838,18 +1900,20 @@ struct drm_i915_cmd_table {
 #define BLT_RING               (1<<BCS)
 #define VEBOX_RING             (1<<VECS)
 #define BSD2_RING              (1<<VCS2)
-#define HAS_BSD(dev)            (INTEL_INFO(dev)->ring_mask & BSD_RING)
+#define HAS_BSD(dev)           (INTEL_INFO(dev)->ring_mask & BSD_RING)
 #define HAS_BSD2(dev)          (INTEL_INFO(dev)->ring_mask & BSD2_RING)
-#define HAS_BLT(dev)            (INTEL_INFO(dev)->ring_mask & BLT_RING)
-#define HAS_VEBOX(dev)            (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
-#define HAS_LLC(dev)            (INTEL_INFO(dev)->has_llc)
-#define HAS_WT(dev)            (IS_HASWELL(dev) && to_i915(dev)->ellc_size)
+#define HAS_BLT(dev)           (INTEL_INFO(dev)->ring_mask & BLT_RING)
+#define HAS_VEBOX(dev)         (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
+#define HAS_LLC(dev)           (INTEL_INFO(dev)->has_llc)
+#define HAS_WT(dev)            ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
+                                to_i915(dev)->ellc_size)
 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
 
 #define HAS_HW_CONTEXTS(dev)   (INTEL_INFO(dev)->gen >= 6)
-#define HAS_ALIASING_PPGTT(dev)        (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev))
-#define HAS_PPGTT(dev)         (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) \
-                                && !IS_BROADWELL(dev))
+#define HAS_ALIASING_PPGTT(dev)        (INTEL_INFO(dev)->gen >= 6 && \
+                                (!IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
+#define HAS_PPGTT(dev)         (INTEL_INFO(dev)->gen >= 7 \
+                                && !IS_GEN8(dev))
 #define USES_PPGTT(dev)                intel_enable_ppgtt(dev, false)
 #define USES_FULL_PPGTT(dev)   intel_enable_ppgtt(dev, true)
 
@@ -1888,7 +1952,7 @@ struct drm_i915_cmd_table {
 #define HAS_FPGA_DBG_UNCLAIMED(dev)    (INTEL_INFO(dev)->has_fpga_dbg)
 #define HAS_PSR(dev)           (IS_HASWELL(dev) || IS_BROADWELL(dev))
 #define HAS_RUNTIME_PM(dev)    (IS_GEN6(dev) || IS_HASWELL(dev) || \
-                                IS_BROADWELL(dev))
+                                IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
 
 #define INTEL_PCH_DEVICE_ID_MASK               0xff00
 #define INTEL_PCH_IBX_DEVICE_ID_TYPE           0x3b00
@@ -1974,6 +2038,7 @@ extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
+int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
 
 extern void intel_console_resume(struct work_struct *work);
 
@@ -2150,6 +2215,7 @@ struct drm_i915_gem_request *
 i915_gem_find_active_request(struct intel_ring_buffer *ring);
 
 bool i915_gem_retire_requests(struct drm_device *dev);
+void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
                                      bool interruptible);
 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
@@ -2418,7 +2484,8 @@ const char *i915_cache_level_str(int type);
 
 /* i915_cmd_parser.c */
 int i915_cmd_parser_get_version(void);
-void i915_cmd_parser_init_ring(struct intel_ring_buffer *ring);
+int i915_cmd_parser_init_ring(struct intel_ring_buffer *ring);
+void i915_cmd_parser_fini_ring(struct intel_ring_buffer *ring);
 bool i915_needs_cmd_parser(struct intel_ring_buffer *ring);
 int i915_parse_cmds(struct intel_ring_buffer *ring,
                    struct drm_i915_gem_object *batch_obj,