drm/i915: Type safe register read/write

[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_drv.h

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 358c9d598e6dfacce37af980ff5d79cb5824c6b3..aba115fefd1f803532ea816d8ad2ba3302a09f78 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -685,18 +685,18 @@ struct intel_uncore_funcs {
        void (*force_wake_put)(struct drm_i915_private *dev_priv,
                                                        enum forcewake_domains domains);
 
-       uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
-       uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
-       uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
-       uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
+       uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
+       uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
+       uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
+       uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
 
-       void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
+       void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
                                uint8_t val, bool trace);
-       void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
+       void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
                                uint16_t val, bool trace);
-       void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
+       void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
                                uint32_t val, bool trace);
-       void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
+       void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r,
                                uint64_t val, bool trace);
 };
 
@@ -713,11 +713,11 @@ struct intel_uncore {
                enum forcewake_domain_id id;
                unsigned wake_count;
                struct timer_list timer;
-               u32 reg_set;
+               i915_reg_t reg_set;
                u32 val_set;
                u32 val_clear;
-               u32 reg_ack;
-               u32 reg_post;
+               i915_reg_t reg_ack;
+               i915_reg_t reg_post;
                u32 val_reset;
        } fw_domain[FW_DOMAIN_ID_COUNT];
 };
@@ -743,7 +743,7 @@ struct intel_csr {
        uint32_t dmc_fw_size;
        uint32_t version;
        uint32_t mmio_count;
-       uint32_t mmioaddr[8];
+       i915_reg_t mmioaddr[8];
        uint32_t mmiodata[8];
 };
 
@@ -996,7 +996,7 @@ struct intel_gmbus {
        struct i2c_adapter adapter;
        u32 force_bit;
        u32 reg0;
-       u32 gpio_reg;
+       i915_reg_t gpio_reg;
        struct i2c_algo_bit_data bit_algo;
        struct drm_i915_private *dev_priv;
 };
@@ -1645,7 +1645,7 @@ struct i915_frontbuffer_tracking {
 };
 
 struct i915_wa_reg {
-       u32 addr;
+       i915_reg_t addr;
        u32 value;
        /* bitmask representing WA bits */
        u32 mask;
@@ -3434,16 +3434,16 @@ int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
 
 #define __raw_read(x, s) \
 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
-                                            uint32_t reg) \
+                                            i915_reg_t reg) \
 { \
-       return read##s(dev_priv->regs + reg); \
+       return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
 }
 
 #define __raw_write(x, s) \
 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
-                                      uint32_t reg, uint##x##_t val) \
+                                      i915_reg_t reg, uint##x##_t val) \
 { \
-       write##s(val, dev_priv->regs + reg); \
+       write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
 }
 __raw_read(8, b)
 __raw_read(16, w)
@@ -3474,7 +3474,7 @@ __raw_write(64, q)
 #define INTEL_BROADCAST_RGB_FULL 1
 #define INTEL_BROADCAST_RGB_LIMITED 2
 
-static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
+static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
 {
        if (IS_VALLEYVIEW(dev))
                return VLV_VGACNTRL;