drm/i915: vlv: add runtime PM support
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_drv.h
index 6d7aa686168be796bd57b45633f5b37fe81fe73e..b54cef419b2bc26d186e46b5626e8bcdf9edbcc5 100644 (file)
@@ -819,6 +819,67 @@ struct i915_suspend_saved_registers {
        u32 savePCH_PORT_HOTPLUG;
 };
 
+struct vlv_s0ix_state {
+       /* GAM */
+       u32 wr_watermark;
+       u32 gfx_prio_ctrl;
+       u32 arb_mode;
+       u32 gfx_pend_tlb0;
+       u32 gfx_pend_tlb1;
+       u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
+       u32 media_max_req_count;
+       u32 gfx_max_req_count;
+       u32 render_hwsp;
+       u32 ecochk;
+       u32 bsd_hwsp;
+       u32 blt_hwsp;
+       u32 tlb_rd_addr;
+
+       /* MBC */
+       u32 g3dctl;
+       u32 gsckgctl;
+       u32 mbctl;
+
+       /* GCP */
+       u32 ucgctl1;
+       u32 ucgctl3;
+       u32 rcgctl1;
+       u32 rcgctl2;
+       u32 rstctl;
+       u32 misccpctl;
+
+       /* GPM */
+       u32 gfxpause;
+       u32 rpdeuhwtc;
+       u32 rpdeuc;
+       u32 ecobus;
+       u32 pwrdwnupctl;
+       u32 rp_down_timeout;
+       u32 rp_deucsw;
+       u32 rcubmabdtmr;
+       u32 rcedata;
+       u32 spare2gh;
+
+       /* Display 1 CZ domain */
+       u32 gt_imr;
+       u32 gt_ier;
+       u32 pm_imr;
+       u32 pm_ier;
+       u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
+
+       /* GT SA CZ domain */
+       u32 tilectl;
+       u32 gt_fifoctl;
+       u32 gtlc_wake_ctrl;
+       u32 gtlc_survive;
+       u32 pmwgicz;
+
+       /* Display 2 CZ domain */
+       u32 gu_ctl0;
+       u32 gu_ctl1;
+       u32 clock_gate_dis2;
+};
+
 struct intel_gen6_power_mgmt {
        /* work and pm_iir are protected by dev_priv->irq_lock */
        struct work_struct work;
@@ -1448,6 +1509,7 @@ struct drm_i915_private {
 
        u32 suspend_count;
        struct i915_suspend_saved_registers regfile;
+       struct vlv_s0ix_state vlv_s0ix_state;
 
        struct {
                /*
This page took 0.055856 seconds and 5 git commands to generate.