drm/i915: Put the mm in the parent address space

[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gem.c

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 1246dfd5ff924084270ad3977d9f1fe0ef8cfe86..8f37229a3b52f469a704b4d52dfc0aec0e7370d2 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -181,7 +181,7 @@ i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
                        pinned += i915_gem_obj_ggtt_size(obj);
        mutex_unlock(&dev->struct_mutex);
 
-       args->aper_size = dev_priv->gtt.total;
+       args->aper_size = dev_priv->gtt.base.total;
        args->aper_available_size = args->aper_size - pinned;
 
        return 0;
@@ -2083,10 +2083,8 @@ int __i915_add_request(struct intel_ring_buffer *ring,
        ring->outstanding_lazy_request = 0;
 
        if (!dev_priv->ums.mm_suspended) {
-               if (i915_enable_hangcheck) {
-                       mod_timer(&dev_priv->gpu_error.hangcheck_timer,
-                                 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
-               }
+               i915_queue_hangcheck(ring->dev);
+
                if (was_empty) {
                        queue_delayed_work(dev_priv->wq,
                                           &dev_priv->mm.retire_work,
@@ -3081,7 +3079,7 @@ i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
        u32 size, fence_size, fence_alignment, unfenced_alignment;
        bool mappable, fenceable;
        size_t gtt_max = map_and_fenceable ?
-               dev_priv->gtt.mappable_end : dev_priv->gtt.total;
+               dev_priv->gtt.mappable_end : dev_priv->gtt.base.total;
        int ret;
 
        fence_size = i915_gem_get_gtt_size(dev,
@@ -3123,7 +3121,7 @@ i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
        i915_gem_object_pin_pages(obj);
 
 search_free:
-       ret = drm_mm_insert_node_in_range_generic(&dev_priv->mm.gtt_space,
+       ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
                                                  &obj->gtt_space,
                                                  size, alignment,
                                                  obj->cache_level, 0, gtt_max);
@@ -4147,7 +4145,7 @@ i915_gem_init_hw(struct drm_device *dev)
        if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
                return -EIO;
 
-       if (IS_HASWELL(dev) && (I915_READ(HSW_EDRAM_PRESENT) == 1))
+       if (dev_priv->ellc_size)
                I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
 
        if (HAS_PCH_NOP(dev)) {