drm/i915: Add dev to ppgtt

[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gem_gtt.c

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index c040aad0cca6652f64ae1198e2ce8868a9e300ea..ed0fe15a41f461ab79a2427457d4d197118d17e7 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -77,6 +77,7 @@ int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
        if (!ppgtt)
                return ret;
 
+       ppgtt->dev = dev;
        ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES;
        ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries,
                                  GFP_KERNEL);
@@ -218,7 +219,7 @@ void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
        switch (cache_level) {
        case I915_CACHE_LLC_MLC:
                /* Haswell doesn't set L3 this way */
-               if (IS_HASWELL(obj->base.dev))
+               if (IS_HASWELL(ppgtt->dev))
                        pte_flags |= GEN6_PTE_CACHE_LLC;
                else
                        pte_flags |= GEN6_PTE_CACHE_LLC_MLC;
@@ -227,7 +228,7 @@ void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
                pte_flags |= GEN6_PTE_CACHE_LLC;
                break;
        case I915_CACHE_NONE:
-               if (IS_HASWELL(obj->base.dev))
+               if (IS_HASWELL(ppgtt->dev))
                        pte_flags |= HSW_PTE_UNCACHED;
                else
                        pte_flags |= GEN6_PTE_UNCACHED;