drm/i915: Added write-enable pte bit supportt

[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gem_gtt.h

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 1b96a06be3cb4f4872103c04d437e966c7b10f4f..8d6f7c18c40413bf46288bec1144d26b5fc652dc 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -154,6 +154,7 @@ struct i915_vma {
        void (*unbind_vma)(struct i915_vma *vma);
        /* Map an object into an address space with the given cache flags. */
 #define GLOBAL_BIND (1<<0)
+#define PTE_READ_ONLY (1<<1)
        void (*bind_vma)(struct i915_vma *vma,
                         enum i915_cache_level cache_level,
                         u32 flags);
@@ -197,7 +198,7 @@ struct i915_address_space {
        /* FIXME: Need a more generic return type */
        gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr,
                                     enum i915_cache_level level,
-                                    bool valid); /* Create a valid PTE */
+                                    bool valid, u32 flags); /* Create a valid PTE */
        void (*clear_range)(struct i915_address_space *vm,
                            uint64_t start,
                            uint64_t length,
@@ -205,7 +206,7 @@ struct i915_address_space {
        void (*insert_entries)(struct i915_address_space *vm,
                               struct sg_table *st,
                               uint64_t start,
-                              enum i915_cache_level cache_level);
+                              enum i915_cache_level cache_level, u32 flags);
        void (*cleanup)(struct i915_address_space *vm);
 };