drm/i915: Added write-enable pte bit supportt
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gem_gtt.h
index b5e8ac0f5ce4ddb291ccbc7dd384715b2e5b6498..8d6f7c18c40413bf46288bec1144d26b5fc652dc 100644 (file)
@@ -95,6 +95,7 @@ typedef gen8_gtt_pte_t gen8_ppgtt_pde_t;
 #define PPAT_CACHED_INDEX              _PAGE_PAT /* WB LLCeLLC */
 #define PPAT_DISPLAY_ELLC_INDEX                _PAGE_PCD /* WT eLLC */
 
+#define CHV_PPAT_SNOOP                 (1<<6)
 #define GEN8_PPAT_AGE(x)               (x<<4)
 #define GEN8_PPAT_LLCeLLC              (3<<2)
 #define GEN8_PPAT_LLCELLC              (2<<2)
@@ -153,6 +154,7 @@ struct i915_vma {
        void (*unbind_vma)(struct i915_vma *vma);
        /* Map an object into an address space with the given cache flags. */
 #define GLOBAL_BIND (1<<0)
+#define PTE_READ_ONLY (1<<1)
        void (*bind_vma)(struct i915_vma *vma,
                         enum i915_cache_level cache_level,
                         u32 flags);
@@ -196,7 +198,7 @@ struct i915_address_space {
        /* FIXME: Need a more generic return type */
        gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr,
                                     enum i915_cache_level level,
-                                    bool valid); /* Create a valid PTE */
+                                    bool valid, u32 flags); /* Create a valid PTE */
        void (*clear_range)(struct i915_address_space *vm,
                            uint64_t start,
                            uint64_t length,
@@ -204,7 +206,7 @@ struct i915_address_space {
        void (*insert_entries)(struct i915_address_space *vm,
                               struct sg_table *st,
                               uint64_t start,
-                              enum i915_cache_level cache_level);
+                              enum i915_cache_level cache_level, u32 flags);
        void (*cleanup)(struct i915_address_space *vm);
 };
 
@@ -256,11 +258,11 @@ struct i915_hw_ppgtt {
                dma_addr_t *gen8_pt_dma_addr[4];
        };
 
-       struct i915_hw_context *ctx;
+       struct intel_context *ctx;
 
        int (*enable)(struct i915_hw_ppgtt *ppgtt);
        int (*switch_mm)(struct i915_hw_ppgtt *ppgtt,
-                        struct intel_ring_buffer *ring,
+                        struct intel_engine_cs *ring,
                         bool synchronous);
        void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m);
 };
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