drm/i915/bdw: New source and header file for LRs, LRCs and Execlists

[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_reg.h

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fbdb08f4cd76e417bdaa79a2227363ce1dafc5da..7a6cc69cdc2b6eb6a8e97b95f82d27130e1d51d2 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1697,12 +1697,9 @@ enum punit_power_well {
 #define DPIO_PHY_STATUS                        (VLV_DISPLAY_BASE + 0x6240)
 #define   DPLL_PORTD_READY_MASK                (0xf)
 #define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100)
-#define   PHY_COM_LANE_RESET_DEASSERT(phy, val) \
-                               ((phy == DPIO_PHY0) ? (val | 1) : (val | 2))
-#define   PHY_COM_LANE_RESET_ASSERT(phy, val) \
-                               ((phy == DPIO_PHY0) ? (val & ~1) : (val & ~2))
+#define   PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
 #define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104)
-#define   PHY_POWERGOOD(phy)   ((phy == DPIO_PHY0) ? (1<<31) : (1<<30))
+#define   PHY_POWERGOOD(phy)   (((phy) == DPIO_PHY0) ? (1<<31) : (1<<30))
 
 /*
  * The i830 generation, in LVDS mode, defines P1 as the bit number set within
@@ -4003,15 +4000,13 @@ enum punit_power_well {
 #define DDL_CURSOR_PRECISION_64                (1<<31)
 #define DDL_CURSOR_PRECISION_32                (0<<31)
 #define DDL_CURSOR_SHIFT               24
-#define DDL_SPRITE1_PRECISION_64       (1<<23)
-#define DDL_SPRITE1_PRECISION_32       (0<<23)
-#define DDL_SPRITE1_SHIFT              16
-#define DDL_SPRITE0_PRECISION_64       (1<<15)
-#define DDL_SPRITE0_PRECISION_32       (0<<15)
-#define DDL_SPRITE0_SHIFT              8
+#define DDL_SPRITE_PRECISION_64(sprite)        (1<<(15+8*(sprite)))
+#define DDL_SPRITE_PRECISION_32(sprite)        (0<<(15+8*(sprite)))
+#define DDL_SPRITE_SHIFT(sprite)       (8+8*(sprite))
 #define DDL_PLANE_PRECISION_64         (1<<7)
 #define DDL_PLANE_PRECISION_32         (0<<7)
 #define DDL_PLANE_SHIFT                        0
+#define DRAIN_LATENCY_MASK             0x7f
 
 /* FIFO watermark sizes etc */
 #define G4X_FIFO_LINE_SIZE     64