drm/i915: Set up the documented clock gating on Sandybridge and Ironlake.

[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_reg.h

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2720bc2cd678bf4e606086175dbc52cfdb3a9c66..cbbf59f56dfa93c23008e4c98d0b38353a65a6a7 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2176,6 +2176,14 @@
 #define DISPLAY_PORT_PLL_BIOS_1         0x46010
 #define DISPLAY_PORT_PLL_BIOS_2         0x46014
 
+#define PCH_DSPCLK_GATE_D      0x42020
+# define DPFDUNIT_CLOCK_GATE_DISABLE           (1 << 7)
+# define DPARBUNIT_CLOCK_GATE_DISABLE          (1 << 5)
+
+#define PCH_3DCGDIS0           0x46020
+# define MARIUNIT_CLOCK_GATE_DISABLE           (1 << 18)
+# define SVSMUNIT_CLOCK_GATE_DISABLE           (1 << 1)
+
 #define FDI_PLL_FREQ_CTL        0x46030
 #define  FDI_PLL_FREQ_CHANGE_REQUEST    (1<<24)
 #define  FDI_PLL_FREQ_LOCK_LIMIT_MASK   0xfff00