drm/i915/chv: Don't use PCS group access reads
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_reg.h
index 5d1d287f1e3811d568307a74398d3173e7997eb4..eba35bcca2ac749f511aba42135a313f20afe7d3 100644 (file)
@@ -659,6 +659,13 @@ enum punit_power_well {
 #define   DPIO_PCS_TX_LANE1_RESET      (1<<7)
 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
 
+#define _VLV_PCS01_DW0_CH0             0x200
+#define _VLV_PCS23_DW0_CH0             0x400
+#define _VLV_PCS01_DW0_CH1             0x2600
+#define _VLV_PCS23_DW0_CH1             0x2800
+#define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
+#define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
+
 #define _VLV_PCS_DW1_CH0               0x8204
 #define _VLV_PCS_DW1_CH1               0x8404
 #define   CHV_PCS_REQ_SOFTRESET_EN     (1<<23)
@@ -668,6 +675,13 @@ enum punit_power_well {
 #define   DPIO_PCS_CLK_SOFT_RESET      (1<<5)
 #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
 
+#define _VLV_PCS01_DW1_CH0             0x204
+#define _VLV_PCS23_DW1_CH0             0x404
+#define _VLV_PCS01_DW1_CH1             0x2604
+#define _VLV_PCS23_DW1_CH1             0x2804
+#define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
+#define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
+
 #define _VLV_PCS_DW8_CH0               0x8220
 #define _VLV_PCS_DW8_CH1               0x8420
 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
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