drm/i915: export error state ref handling

[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_sysfs.c

diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index d5e1890678f9e61d551af21484dd2233fd8e817c..6875b5654c63d55a65dcf639734e0de101f1f037 100644 (file)
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -212,7 +212,13 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
        int ret;
 
        mutex_lock(&dev_priv->rps.hw_lock);
-       ret = dev_priv->rps.cur_delay * GT_FREQUENCY_MULTIPLIER;
+       if (IS_VALLEYVIEW(dev_priv->dev)) {
+               u32 freq;
+               freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+               ret = vlv_gpu_freq(dev_priv->mem_freq, (freq >> 8) & 0xff);
+       } else {
+               ret = dev_priv->rps.cur_delay * GT_FREQUENCY_MULTIPLIER;
+       }
        mutex_unlock(&dev_priv->rps.hw_lock);
 
        return snprintf(buf, PAGE_SIZE, "%d\n", ret);
@@ -226,7 +232,10 @@ static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute
        int ret;
 
        mutex_lock(&dev_priv->rps.hw_lock);
-       ret = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
+       if (IS_VALLEYVIEW(dev_priv->dev))
+               ret = vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.max_delay);
+       else
+               ret = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
        mutex_unlock(&dev_priv->rps.hw_lock);
 
        return snprintf(buf, PAGE_SIZE, "%d\n", ret);
@@ -246,16 +255,25 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
        if (ret)
                return ret;
 
-       val /= GT_FREQUENCY_MULTIPLIER;
-
        mutex_lock(&dev_priv->rps.hw_lock);
 
-       rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
-       hw_max = dev_priv->rps.hw_max;
-       non_oc_max = (rp_state_cap & 0xff);
-       hw_min = ((rp_state_cap & 0xff0000) >> 16);
+       if (IS_VALLEYVIEW(dev_priv->dev)) {
+               val = vlv_freq_opcode(dev_priv->mem_freq, val);
+
+               hw_max = valleyview_rps_max_freq(dev_priv);
+               hw_min = valleyview_rps_min_freq(dev_priv);
+               non_oc_max = hw_max;
+       } else {
+               val /= GT_FREQUENCY_MULTIPLIER;
+
+               rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
+               hw_max = dev_priv->rps.hw_max;
+               non_oc_max = (rp_state_cap & 0xff);
+               hw_min = ((rp_state_cap & 0xff0000) >> 16);
+       }
 
-       if (val < hw_min || val > hw_max || val < dev_priv->rps.min_delay) {
+       if (val < hw_min || val > hw_max ||
+           val < dev_priv->rps.min_delay) {
                mutex_unlock(&dev_priv->rps.hw_lock);
                return -EINVAL;
        }
@@ -264,8 +282,12 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
                DRM_DEBUG("User requested overclocking to %d\n",
                          val * GT_FREQUENCY_MULTIPLIER);
 
-       if (dev_priv->rps.cur_delay > val)
-               gen6_set_rps(dev_priv->dev, val);
+       if (dev_priv->rps.cur_delay > val) {
+               if (IS_VALLEYVIEW(dev_priv->dev))
+                       valleyview_set_rps(dev_priv->dev, val);
+               else
+                       gen6_set_rps(dev_priv->dev, val);
+       }
 
        dev_priv->rps.max_delay = val;
 
@@ -282,7 +304,10 @@ static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute
        int ret;
 
        mutex_lock(&dev_priv->rps.hw_lock);
-       ret = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
+       if (IS_VALLEYVIEW(dev_priv->dev))
+               ret = vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.min_delay);
+       else
+               ret = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
        mutex_unlock(&dev_priv->rps.hw_lock);
 
        return snprintf(buf, PAGE_SIZE, "%d\n", ret);
@@ -302,21 +327,32 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
        if (ret)
                return ret;
 
-       val /= GT_FREQUENCY_MULTIPLIER;
-
        mutex_lock(&dev_priv->rps.hw_lock);
 
-       rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
-       hw_max = dev_priv->rps.hw_max;
-       hw_min = ((rp_state_cap & 0xff0000) >> 16);
+       if (IS_VALLEYVIEW(dev)) {
+               val = vlv_freq_opcode(dev_priv->mem_freq, val);
+
+               hw_max = valleyview_rps_max_freq(dev_priv);
+               hw_min = valleyview_rps_min_freq(dev_priv);
+       } else {
+               val /= GT_FREQUENCY_MULTIPLIER;
+
+               rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
+               hw_max = dev_priv->rps.hw_max;
+               hw_min = ((rp_state_cap & 0xff0000) >> 16);
+       }
 
        if (val < hw_min || val > hw_max || val > dev_priv->rps.max_delay) {
                mutex_unlock(&dev_priv->rps.hw_lock);
                return -EINVAL;
        }
 
-       if (dev_priv->rps.cur_delay < val)
-               gen6_set_rps(dev_priv->dev, val);
+       if (dev_priv->rps.cur_delay < val) {
+               if (IS_VALLEYVIEW(dev))
+                       valleyview_set_rps(dev, val);
+               else
+                       gen6_set_rps(dev_priv->dev, val);
+       }
 
        dev_priv->rps.min_delay = val;