drm/i915/chv: Update Cherryview DPLL changes to support Port D. v2

[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 63055f1244d03d54f994e896d0b26f0a7e1a149b..c42593fd53a5c89e446650631b33d3d7c17c55ce 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1535,21 +1535,28 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
                struct intel_digital_port *dport)
 {
        u32 port_mask;
+       int dpll_reg;
 
        switch (dport->port) {
        case PORT_B:
                port_mask = DPLL_PORTB_READY_MASK;
+               dpll_reg = DPLL(0);
                break;
        case PORT_C:
                port_mask = DPLL_PORTC_READY_MASK;
+               dpll_reg = DPLL(0);
+               break;
+       case PORT_D:
+               port_mask = DPLL_PORTD_READY_MASK;
+               dpll_reg = DPIO_PHY_STATUS;
                break;
        default:
                BUG();
        }
 
-       if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
+       if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
                WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
-                    port_name(dport->port), I915_READ(DPLL(0)));
+                    port_name(dport->port), I915_READ(dpll_reg));
 }
 
 /**