drm/i915: Fix MST link rate handling

[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp_mst.c

diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index be124928ca143c3e435cf8cfdb3916a4030e24fb..7e6f12597a6cbc257c52aa677f9474d7b1d2ba5b 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -38,7 +38,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
        struct intel_dp *intel_dp = &intel_dig_port->dp;
        struct drm_device *dev = encoder->base.dev;
        int bpp;
-       int lane_count, slots;
+       int lane_count, slots, rate;
        struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
        struct intel_connector *found = NULL, *intel_connector;
        int mst_pbn;
@@ -52,11 +52,21 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
         * seem to suggest we should do otherwise.
         */
        lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
-       intel_dp->link_bw = intel_dp_max_link_bw(intel_dp);
+
+       rate = intel_dp_max_link_rate(intel_dp);
+
+       if (intel_dp->num_supported_rates) {
+               intel_dp->link_bw = 0;
+               intel_dp->rate_select = intel_dp_rate_select(intel_dp, rate);
+       } else {
+               intel_dp->link_bw = drm_dp_link_rate_to_bw_code(rate);
+               intel_dp->rate_select = 0;
+       }
+
        intel_dp->lane_count = lane_count;
 
        pipe_config->pipe_bpp = 24;
-       pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
+       pipe_config->port_clock = rate;
 
        for_each_intel_connector(dev, intel_connector) {
                if (intel_connector->new_encoder == encoder) {