drm/i915: Don't enable IPS when pixel rate exceeds 95%

[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_drv.h

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 980b3aff9bf415e8184346bfe7e0f6a665e59d1c..5cb30044acf48448ab5280be3f0ffbdffcf35e06 100644 (file)
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -248,12 +248,6 @@ struct intel_plane_state {
        struct drm_rect clip;
        bool visible;
 
-       /*
-        * used only for sprite planes to determine when to implicitly
-        * enable/disable the primary plane
-        */
-       bool hides_primary;
-
        /*
         * scaler_id
         *    = -1 : not using a scaler
@@ -465,8 +459,10 @@ struct intel_pipe_wm {
 };
 
 struct intel_mmio_flip {
-       struct drm_i915_gem_request *req;
        struct work_struct work;
+       struct drm_i915_private *i915;
+       struct drm_i915_gem_request *req;
+       struct intel_crtc *crtc;
 };
 
 struct skl_pipe_wm {
@@ -513,7 +509,6 @@ struct intel_crtc {
         */
        bool active;
        unsigned long enabled_power_domains;
-       bool primary_enabled; /* is the primary plane (partially) visible? */
        bool lowfreq_avail;
        struct intel_overlay *overlay;
        struct intel_unpin_work *unpin_work;
@@ -551,7 +546,6 @@ struct intel_crtc {
        } wm;
 
        int scanline_offset;
-       struct intel_mmio_flip mmio_flip;
 
        struct intel_crtc_atomic_commit atomic;
 
@@ -562,7 +556,15 @@ struct intel_crtc {
 struct intel_plane_wm_parameters {
        uint32_t horiz_pixels;
        uint32_t vert_pixels;
+       /*
+        *   For packed pixel formats:
+        *     bytes_per_pixel - holds bytes per pixel
+        *   For planar pixel formats:
+        *     bytes_per_pixel - holds bytes per pixel for uv-plane
+        *     y_bytes_per_pixel - holds bytes per pixel for y-plane
+        */
        uint8_t bytes_per_pixel;
+       uint8_t y_bytes_per_pixel;
        bool enabled;
        bool scaled;
        u64 tiling;
@@ -600,7 +602,7 @@ struct intel_plane {
                             uint32_t x, uint32_t y,
                             uint32_t src_w, uint32_t src_h);
        void (*disable_plane)(struct drm_plane *plane,
-                             struct drm_crtc *crtc);
+                             struct drm_crtc *crtc, bool force);
        int (*check_plane)(struct drm_plane *plane,
                           struct intel_plane_state *state);
        void (*commit_plane)(struct drm_plane *plane,
@@ -736,9 +738,12 @@ struct intel_dp {
                                     bool has_aux_irq,
                                     int send_bytes,
                                     uint32_t aux_clock_divider);
+       bool train_set_valid;
 
        /* Displayport compliance testing */
        unsigned long compliance_test_type;
+       unsigned long compliance_test_data;
+       bool compliance_test_active;
 };
 
 struct intel_digital_port {
@@ -817,15 +822,6 @@ struct intel_unpin_work {
        bool enable_stall_check;
 };
 
-struct intel_set_config {
-       struct drm_encoder **save_connector_encoders;
-       struct drm_crtc **save_encoder_crtcs;
-       bool *save_crtc_enabled;
-
-       bool fb_changed;
-       bool mode_changed;
-};
-
 struct intel_load_detect_pipe {
        struct drm_framebuffer *release_fb;
        bool load_detect_temp;
@@ -998,6 +994,7 @@ void intel_mark_busy(struct drm_device *dev);
 void intel_mark_idle(struct drm_device *dev);
 void intel_crtc_restore_mode(struct drm_crtc *crtc);
 void intel_crtc_control(struct drm_crtc *crtc, bool enable);
+void intel_crtc_reset(struct intel_crtc *crtc);
 void intel_crtc_update_dpms(struct drm_crtc *crtc);
 void intel_encoder_destroy(struct drm_encoder *encoder);
 int intel_connector_init(struct intel_connector *);
@@ -1025,7 +1022,8 @@ intel_wait_for_vblank(struct drm_device *dev, int pipe)
 }
 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
-                        struct intel_digital_port *dport);
+                        struct intel_digital_port *dport,
+                        unsigned int expected_mask);
 bool intel_get_load_detect_pipe(struct drm_connector *connector,
                                struct drm_display_mode *mode,
                                struct intel_load_detect_pipe *old,
@@ -1070,9 +1068,6 @@ intel_rotation_90_or_270(unsigned int rotation)
        return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
 }
 
-unsigned int
-intel_tile_height(struct drm_device *dev, uint32_t bits_per_pixel,
-                 uint64_t fb_modifier);
 void intel_create_rotation_property(struct drm_device *dev,
                                        struct intel_plane *plane);
 
@@ -1123,6 +1118,8 @@ void broxton_ddi_phy_init(struct drm_device *dev);
 void broxton_ddi_phy_uninit(struct drm_device *dev);
 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
+void skl_init_cdclk(struct drm_i915_private *dev_priv);
+void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
 void intel_dp_get_m_n(struct intel_crtc *crtc,
                      struct intel_crtc_state *pipe_config);
 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
@@ -1160,6 +1157,7 @@ void intel_csr_load_status_set(struct drm_i915_private *dev_priv,
                                        enum csr_state state);
 void intel_csr_load_program(struct drm_device *dev);
 void intel_csr_ucode_fini(struct drm_device *dev);
+void assert_csr_loaded(struct drm_i915_private *dev_priv);
 
 /* intel_dp.c */
 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
@@ -1369,14 +1367,15 @@ void gen6_rps_busy(struct drm_i915_private *dev_priv);
 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
 void gen6_rps_idle(struct drm_i915_private *dev_priv);
 void gen6_rps_boost(struct drm_i915_private *dev_priv,
-                   struct drm_i915_file_private *file_priv);
+                   struct intel_rps_client *rps,
+                   unsigned long submitted);
 void intel_queue_rps_boost_for_request(struct drm_device *dev,
-                                      struct drm_i915_gem_request *rq);
+                                      struct drm_i915_gem_request *req);
 void ilk_wm_get_hw_state(struct drm_device *dev);
 void skl_wm_get_hw_state(struct drm_device *dev);
 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
                          struct skl_ddb_allocation *ddb /* out */);
-
+uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
 
 /* intel_sdvo.c */
 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
@@ -1384,16 +1383,12 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
 
 /* intel_sprite.c */
 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
-void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
-                              enum plane plane);
 int intel_plane_restore(struct drm_plane *plane);
 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
                              struct drm_file *file_priv);
 bool intel_pipe_update_start(struct intel_crtc *crtc,
                             uint32_t *start_vbl_count);
 void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count);
-void intel_post_enable_primary(struct drm_crtc *crtc);
-void intel_pre_disable_primary(struct drm_crtc *crtc);
 
 /* intel_tv.c */
 void intel_tv_init(struct drm_device *dev);
@@ -1418,7 +1413,7 @@ intel_atomic_get_crtc_state(struct drm_atomic_state *state,
        struct drm_crtc_state *crtc_state;
        crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
        if (IS_ERR(crtc_state))
-               return ERR_PTR(PTR_ERR(crtc_state));
+               return ERR_CAST(crtc_state);
 
        return to_intel_crtc_state(crtc_state);
 }