drm/i915/chv: Don't use PCS group access reads

[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_hdmi.c

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index f66c7a2ebd9a1335a0cd31d557763cc665b1fdc2..b976255f7961546b12eead625e8d74841ce1d55a 100644 (file)
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1259,13 +1259,21 @@ static void chv_hdmi_post_disable(struct intel_encoder *encoder)
        mutex_lock(&dev_priv->dpio_lock);
 
        /* Propagate soft reset to data lane reset */
-       val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
+       val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
        val |= CHV_PCS_REQ_SOFTRESET_EN;
-       vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
+       vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
 
-       val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
+       val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
+       val |= CHV_PCS_REQ_SOFTRESET_EN;
+       vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
+
+       val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
+       val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
+       vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
+
+       val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
        val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
-       vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
+       vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
 
        mutex_unlock(&dev_priv->dpio_lock);
 }
@@ -1285,13 +1293,21 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
        mutex_lock(&dev_priv->dpio_lock);
 
        /* Deassert soft data lane reset*/
-       val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
+       val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
        val |= CHV_PCS_REQ_SOFTRESET_EN;
-       vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
+       vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
+
+       val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
+       val |= CHV_PCS_REQ_SOFTRESET_EN;
+       vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
+
+       val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
+       val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
+       vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
 
-       val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
+       val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
        val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
-       vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
+       vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
 
        /* Program Tx latency optimal setting */
        for (i = 0; i < 4; i++) {