drm/i915/skl: Move gen9 pm initialization into its own branch

[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4f5dcf545c8989b0e167f865827e0fbb472eb2dc..81eb8bca5628f71e3b6e425afeb69a17a46eca74 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7397,7 +7397,9 @@ void intel_init_pm(struct drm_device *dev)
                i915_ironlake_get_mem_freq(dev);
 
        /* For FIFO watermark updates */
-       if (HAS_PCH_SPLIT(dev)) {
+       if (IS_GEN9(dev)) {
+               dev_priv->display.init_clock_gating = gen9_init_clock_gating;
+       } else if (HAS_PCH_SPLIT(dev)) {
                ilk_setup_wm_latency(dev);
 
                if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
@@ -7421,8 +7423,6 @@ void intel_init_pm(struct drm_device *dev)
                        dev_priv->display.init_clock_gating = haswell_init_clock_gating;
                else if (INTEL_INFO(dev)->gen == 8)
                        dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
-               else if (INTEL_INFO(dev)->gen == 9)
-                       dev_priv->display.init_clock_gating = gen9_init_clock_gating;
        } else if (IS_CHERRYVIEW(dev)) {
                dev_priv->display.update_wm = cherryview_update_wm;
                dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;