drm/i915: Make addressing mode bits in context descriptor configurable

[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_psr.c

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index a788d1e9589b7a47f5b6fd51550be8bba1e8c7a5..29a09bf6bd18666a3225d6e77d93d2bc5504ebde 100644 (file)
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -176,7 +176,6 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
        struct drm_i915_private *dev_priv = dev->dev_private;
        uint32_t aux_clock_divider;
        i915_reg_t aux_ctl_reg;
-       int precharge = 0x3;
        static const uint8_t aux_msg[] = {
                [0] = DP_AUX_NATIVE_WRITE << 4,
                [1] = DP_SET_POWER >> 8,
@@ -185,6 +184,7 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
                [4] = DP_SET_POWER_D0,
        };
        enum port port = dig_port->port;
+       u32 aux_ctl;
        int i;
 
        BUILD_BUG_ON(sizeof(aux_msg) > 20);
@@ -197,6 +197,13 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
                                DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF,
                                DP_AUX_FRAME_SYNC_ENABLE);
 
+       if (dev_priv->psr.link_standby)
+               drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
+                                  DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
+       else
+               drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
+                                  DP_PSR_ENABLE);
+
        aux_ctl_reg = psr_aux_ctl_reg(dev_priv, port);
 
        /* Setup AUX registers */
@@ -204,33 +211,9 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
                I915_WRITE(psr_aux_data_reg(dev_priv, port, i >> 2),
                           intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
 
-       if (INTEL_INFO(dev)->gen >= 9) {
-               uint32_t val;
-
-               val = I915_READ(aux_ctl_reg);
-               val &= ~DP_AUX_CH_CTL_TIME_OUT_MASK;
-               val |= DP_AUX_CH_CTL_TIME_OUT_1600us;
-               val &= ~DP_AUX_CH_CTL_MESSAGE_SIZE_MASK;
-               val |= (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
-               /* Use hardcoded data values for PSR, frame sync and GTC */
-               val &= ~DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL;
-               val &= ~DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL;
-               val &= ~DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL;
-               I915_WRITE(aux_ctl_reg, val);
-       } else {
-               I915_WRITE(aux_ctl_reg,
-                  DP_AUX_CH_CTL_TIME_OUT_400us |
-                  (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
-                  (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
-                  (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
-       }
-
-       if (dev_priv->psr.link_standby)
-               drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
-                                  DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
-       else
-               drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
-                                  DP_PSR_ENABLE);
+       aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, 0, sizeof(aux_msg),
+                                            aux_clock_divider);
+       I915_WRITE(aux_ctl_reg, aux_ctl);
 }
 
 static void vlv_psr_enable_source(struct intel_dp *intel_dp)
@@ -272,14 +255,14 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
        struct drm_i915_private *dev_priv = dev->dev_private;
 
        uint32_t max_sleep_time = 0x1f;
-       /*
-        * Let's respect VBT in case VBT asks a higher idle_frame value.
-        * Let's use 6 as the minimum to cover all known cases including
-        * the off-by-one issue that HW has in some cases. Also there are
-        * cases where sink should be able to train
-        * with the 5 or 6 idle patterns.
+       /* Lately it was identified that depending on panel idle frame count
+        * calculated at HW can be off by 1. So let's use what came
+        * from VBT + 1.
+        * There are also other cases where panel demands at least 4
+        * but VBT is not being set. To cover these 2 cases lets use
+        * at least 5 when VBT isn't set to be on the safest side.
         */
-       uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
+       uint32_t idle_frames = dev_priv->vbt.psr.idle_frames + 1;
        uint32_t val = EDP_PSR_ENABLE;
 
        val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;