drm/nouveau: port all engines to new engine module format

[deliverable/linux.git] / drivers / gpu / drm / nouveau / core / engine / graph / ctxnv50.c

diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv50.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv50.c
index e17c17bfd89e7c2730a2013cdb9989741b0d8904..552fdbd45ebe9e389c9e017d793959a6333a69e4 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv50.c
@@ -20,6 +20,8 @@
  * OTHER DEALINGS IN THE SOFTWARE.
  */
 
+#include <core/gpuobj.h>
+
 #define CP_FLAG_CLEAR                 0
 #define CP_FLAG_SET                   1
 #define CP_FLAG_SWAP_DIRECTION        ((0 * 32) + 0)
@@ -105,8 +107,7 @@
 #define CP_SEEK_1      0x00c000ff
 #define CP_SEEK_2      0x00c800ff
 
-#include "drmP.h"
-#include "nouveau_drv.h"
+#include "nv50.h"
 #include "ctx.h"
 
 #define IS_NVA3F(x) (((x) > 0xa0 && (x) < 0xaa) || (x) == 0xaf)
@@ -175,32 +176,6 @@ static void nv50_graph_construct_xfer2(struct nouveau_grctx *ctx);
 static int
 nv50_grctx_generate(struct nouveau_grctx *ctx)
 {
-       struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
-
-       switch (dev_priv->chipset) {
-       case 0x50:
-       case 0x84:
-       case 0x86:
-       case 0x92:
-       case 0x94:
-       case 0x96:
-       case 0x98:
-       case 0xa0:
-       case 0xa3:
-       case 0xa5:
-       case 0xa8:
-       case 0xaa:
-       case 0xac:
-       case 0xaf:
-               break;
-       default:
-               NV_ERROR(ctx->dev, "I don't know how to make a ctxprog for "
-                                  "your NV%x card.\n", dev_priv->chipset);
-               NV_ERROR(ctx->dev, "Disabling acceleration. Please contact "
-                                  "the devs.\n");
-               return -ENOSYS;
-       }
-
        cp_set (ctx, STATE, RUNNING);
        cp_set (ctx, XFER_SWITCH, ENABLE);
        /* decide whether we're loading/unloading the context */
@@ -278,30 +253,36 @@ nv50_grctx_generate(struct nouveau_grctx *ctx)
 }
 
 void
-nv50_grctx_fill(struct drm_device *dev, struct nouveau_gpuobj *mem)
+nv50_grctx_fill(struct nouveau_device *device, struct nouveau_gpuobj *mem)
 {
        nv50_grctx_generate(&(struct nouveau_grctx) {
-                            .dev = dev,
+                            .device = device,
                             .mode = NOUVEAU_GRCTX_VALS,
                             .data = mem,
                           });
 }
 
 int
-nv50_grctx_init(struct drm_device *dev, u32 *data, u32 max, u32 *len, u32 *cnt)
+nv50_grctx_init(struct nouveau_device *device, u32 *size)
 {
+       u32 *ctxprog = kmalloc(512 * 4, GFP_KERNEL), i;
        struct nouveau_grctx ctx = {
-               .dev = dev,
+               .device = device,
                .mode = NOUVEAU_GRCTX_PROG,
-               .data = data,
-               .ctxprog_max = max
+               .data = ctxprog,
+               .ctxprog_max = 512,
        };
-       int ret;
 
-       ret = nv50_grctx_generate(&ctx);
-       *cnt = ctx.ctxvals_pos * 4;
-       *len = ctx.ctxprog_len;
-       return ret;
+       if (!ctxprog)
+               return -ENOMEM;
+       nv50_grctx_generate(&ctx);
+
+       nv_wr32(device, 0x400324, 0);
+       for (i = 0; i < ctx.ctxprog_len; i++)
+               nv_wr32(device, 0x400328, ctxprog[i]);
+       *size = ctx.ctxvals_pos * 4;
+       kfree(ctxprog);
+       return 0;
 }
 
 /*
@@ -315,36 +296,36 @@ nv50_graph_construct_mmio_ddata(struct nouveau_grctx *ctx);
 static void
 nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
 {
-       struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
+       struct nouveau_device *device = ctx->device;
        int i, j;
        int offset, base;
-       uint32_t units = nv_rd32 (ctx->dev, 0x1540);
+       u32 units = nv_rd32 (ctx->device, 0x1540);
 
        /* 0800: DISPATCH */
        cp_ctx(ctx, 0x400808, 7);
        gr_def(ctx, 0x400814, 0x00000030);
        cp_ctx(ctx, 0x400834, 0x32);
-       if (dev_priv->chipset == 0x50) {
+       if (device->chipset == 0x50) {
                gr_def(ctx, 0x400834, 0xff400040);
                gr_def(ctx, 0x400838, 0xfff00080);
                gr_def(ctx, 0x40083c, 0xfff70090);
                gr_def(ctx, 0x400840, 0xffe806a8);
        }
        gr_def(ctx, 0x400844, 0x00000002);
-       if (IS_NVA3F(dev_priv->chipset))
+       if (IS_NVA3F(device->chipset))
                gr_def(ctx, 0x400894, 0x00001000);
        gr_def(ctx, 0x4008e8, 0x00000003);
        gr_def(ctx, 0x4008ec, 0x00001000);
-       if (dev_priv->chipset == 0x50)
+       if (device->chipset == 0x50)
                cp_ctx(ctx, 0x400908, 0xb);
-       else if (dev_priv->chipset < 0xa0)
+       else if (device->chipset < 0xa0)
                cp_ctx(ctx, 0x400908, 0xc);
        else
                cp_ctx(ctx, 0x400908, 0xe);
 
-       if (dev_priv->chipset >= 0xa0)
+       if (device->chipset >= 0xa0)
                cp_ctx(ctx, 0x400b00, 0x1);
-       if (IS_NVA3F(dev_priv->chipset)) {
+       if (IS_NVA3F(device->chipset)) {
                cp_ctx(ctx, 0x400b10, 0x1);
                gr_def(ctx, 0x400b10, 0x0001629d);
                cp_ctx(ctx, 0x400b20, 0x1);
@@ -358,10 +339,10 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
        gr_def(ctx, 0x400c08, 0x0000fe0c);
 
        /* 1000 */
-       if (dev_priv->chipset < 0xa0) {
+       if (device->chipset < 0xa0) {
                cp_ctx(ctx, 0x401008, 0x4);
                gr_def(ctx, 0x401014, 0x00001000);
-       } else if (!IS_NVA3F(dev_priv->chipset)) {
+       } else if (!IS_NVA3F(device->chipset)) {
                cp_ctx(ctx, 0x401008, 0x5);
                gr_def(ctx, 0x401018, 0x00001000);
        } else {
@@ -372,7 +353,7 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
        /* 1400 */
        cp_ctx(ctx, 0x401400, 0x8);
        cp_ctx(ctx, 0x401424, 0x3);
-       if (dev_priv->chipset == 0x50)
+       if (device->chipset == 0x50)
                gr_def(ctx, 0x40142c, 0x0001fd87);
        else
                gr_def(ctx, 0x40142c, 0x00000187);
@@ -382,10 +363,10 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
        /* 1800: STREAMOUT */
        cp_ctx(ctx, 0x401814, 0x1);
        gr_def(ctx, 0x401814, 0x000000ff);
-       if (dev_priv->chipset == 0x50) {
+       if (device->chipset == 0x50) {
                cp_ctx(ctx, 0x40181c, 0xe);
                gr_def(ctx, 0x401850, 0x00000004);
-       } else if (dev_priv->chipset < 0xa0) {
+       } else if (device->chipset < 0xa0) {
                cp_ctx(ctx, 0x40181c, 0xf);
                gr_def(ctx, 0x401854, 0x00000004);
        } else {
@@ -395,7 +376,7 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
 
        /* 1C00 */
        cp_ctx(ctx, 0x401c00, 0x1);
-       switch (dev_priv->chipset) {
+       switch (device->chipset) {
        case 0x50:
                gr_def(ctx, 0x401c00, 0x0001005f);
                break;
@@ -424,7 +405,7 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
 
        /* 2400 */
        cp_ctx(ctx, 0x402400, 0x1);
-       if (dev_priv->chipset == 0x50)
+       if (device->chipset == 0x50)
                cp_ctx(ctx, 0x402408, 0x1);
        else
                cp_ctx(ctx, 0x402408, 0x2);
@@ -432,21 +413,21 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
 
        /* 2800: CSCHED */
        cp_ctx(ctx, 0x402800, 0x1);
-       if (dev_priv->chipset == 0x50)
+       if (device->chipset == 0x50)
                gr_def(ctx, 0x402800, 0x00000006);
 
        /* 2C00: ZCULL */
        cp_ctx(ctx, 0x402c08, 0x6);
-       if (dev_priv->chipset != 0x50)
+       if (device->chipset != 0x50)
                gr_def(ctx, 0x402c14, 0x01000000);
        gr_def(ctx, 0x402c18, 0x000000ff);
-       if (dev_priv->chipset == 0x50)
+       if (device->chipset == 0x50)
                cp_ctx(ctx, 0x402ca0, 0x1);
        else
                cp_ctx(ctx, 0x402ca0, 0x2);
-       if (dev_priv->chipset < 0xa0)
+       if (device->chipset < 0xa0)
                gr_def(ctx, 0x402ca0, 0x00000400);
-       else if (!IS_NVA3F(dev_priv->chipset))
+       else if (!IS_NVA3F(device->chipset))
                gr_def(ctx, 0x402ca0, 0x00000800);
        else
                gr_def(ctx, 0x402ca0, 0x00000400);
@@ -457,14 +438,14 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
        gr_def(ctx, 0x403004, 0x00000001);
 
        /* 3400 */
-       if (dev_priv->chipset >= 0xa0) {
+       if (device->chipset >= 0xa0) {
                cp_ctx(ctx, 0x403404, 0x1);
                gr_def(ctx, 0x403404, 0x00000001);
        }
 
        /* 5000: CCACHE */
        cp_ctx(ctx, 0x405000, 0x1);
-       switch (dev_priv->chipset) {
+       switch (device->chipset) {
        case 0x50:
                gr_def(ctx, 0x405000, 0x00300080);
                break;
@@ -493,22 +474,22 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
        cp_ctx(ctx, 0x40502c, 0x1);
 
        /* 6000? */
-       if (dev_priv->chipset == 0x50)
+       if (device->chipset == 0x50)
                cp_ctx(ctx, 0x4063e0, 0x1);
 
        /* 6800: M2MF */
-       if (dev_priv->chipset < 0x90) {
+       if (device->chipset < 0x90) {
                cp_ctx(ctx, 0x406814, 0x2b);
                gr_def(ctx, 0x406818, 0x00000f80);
                gr_def(ctx, 0x406860, 0x007f0080);
                gr_def(ctx, 0x40689c, 0x007f0080);
        } else {
                cp_ctx(ctx, 0x406814, 0x4);
-               if (dev_priv->chipset == 0x98)
+               if (device->chipset == 0x98)
                        gr_def(ctx, 0x406818, 0x00000f80);
                else
                        gr_def(ctx, 0x406818, 0x00001f80);
-               if (IS_NVA3F(dev_priv->chipset))
+               if (IS_NVA3F(device->chipset))
                        gr_def(ctx, 0x40681c, 0x00000030);
                cp_ctx(ctx, 0x406830, 0x3);
        }
@@ -517,43 +498,43 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
        for (i = 0; i < 8; i++) {
                if (units & (1<<(i+16))) {
                        cp_ctx(ctx, 0x407000 + (i<<8), 3);
-                       if (dev_priv->chipset == 0x50)
+                       if (device->chipset == 0x50)
                                gr_def(ctx, 0x407000 + (i<<8), 0x1b74f820);
-                       else if (dev_priv->chipset != 0xa5)
+                       else if (device->chipset != 0xa5)
                                gr_def(ctx, 0x407000 + (i<<8), 0x3b74f821);
                        else
                                gr_def(ctx, 0x407000 + (i<<8), 0x7b74f821);
                        gr_def(ctx, 0x407004 + (i<<8), 0x89058001);
 
-                       if (dev_priv->chipset == 0x50) {
+                       if (device->chipset == 0x50) {
                                cp_ctx(ctx, 0x407010 + (i<<8), 1);
-                       } else if (dev_priv->chipset < 0xa0) {
+                       } else if (device->chipset < 0xa0) {
                                cp_ctx(ctx, 0x407010 + (i<<8), 2);
                                gr_def(ctx, 0x407010 + (i<<8), 0x00001000);
                                gr_def(ctx, 0x407014 + (i<<8), 0x0000001f);
                        } else {
                                cp_ctx(ctx, 0x407010 + (i<<8), 3);
                                gr_def(ctx, 0x407010 + (i<<8), 0x00001000);
-                               if (dev_priv->chipset != 0xa5)
+                               if (device->chipset != 0xa5)
                                        gr_def(ctx, 0x407014 + (i<<8), 0x000000ff);
                                else
                                        gr_def(ctx, 0x407014 + (i<<8), 0x000001ff);
                        }
 
                        cp_ctx(ctx, 0x407080 + (i<<8), 4);
-                       if (dev_priv->chipset != 0xa5)
+                       if (device->chipset != 0xa5)
                                gr_def(ctx, 0x407080 + (i<<8), 0x027c10fa);
                        else
                                gr_def(ctx, 0x407080 + (i<<8), 0x827c10fa);
-                       if (dev_priv->chipset == 0x50)
+                       if (device->chipset == 0x50)
                                gr_def(ctx, 0x407084 + (i<<8), 0x000000c0);
                        else
                                gr_def(ctx, 0x407084 + (i<<8), 0x400000c0);
                        gr_def(ctx, 0x407088 + (i<<8), 0xb7892080);
 
-                       if (dev_priv->chipset < 0xa0)
+                       if (device->chipset < 0xa0)
                                cp_ctx(ctx, 0x407094 + (i<<8), 1);
-                       else if (!IS_NVA3F(dev_priv->chipset))
+                       else if (!IS_NVA3F(device->chipset))
                                cp_ctx(ctx, 0x407094 + (i<<8), 3);
                        else {
                                cp_ctx(ctx, 0x407094 + (i<<8), 4);
@@ -563,30 +544,30 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
        }
 
        cp_ctx(ctx, 0x407c00, 0x3);
-       if (dev_priv->chipset < 0x90)
+       if (device->chipset < 0x90)
                gr_def(ctx, 0x407c00, 0x00010040);
-       else if (dev_priv->chipset < 0xa0)
+       else if (device->chipset < 0xa0)
                gr_def(ctx, 0x407c00, 0x00390040);
        else
                gr_def(ctx, 0x407c00, 0x003d0040);
        gr_def(ctx, 0x407c08, 0x00000022);
-       if (dev_priv->chipset >= 0xa0) {
+       if (device->chipset >= 0xa0) {
                cp_ctx(ctx, 0x407c10, 0x3);
                cp_ctx(ctx, 0x407c20, 0x1);
                cp_ctx(ctx, 0x407c2c, 0x1);
        }
 
-       if (dev_priv->chipset < 0xa0) {
+       if (device->chipset < 0xa0) {
                cp_ctx(ctx, 0x407d00, 0x9);
        } else {
                cp_ctx(ctx, 0x407d00, 0x15);
        }
-       if (dev_priv->chipset == 0x98)
+       if (device->chipset == 0x98)
                gr_def(ctx, 0x407d08, 0x00380040);
        else {
-               if (dev_priv->chipset < 0x90)
+               if (device->chipset < 0x90)
                        gr_def(ctx, 0x407d08, 0x00010040);
-               else if (dev_priv->chipset < 0xa0)
+               else if (device->chipset < 0xa0)
                        gr_def(ctx, 0x407d08, 0x00390040);
                else
                        gr_def(ctx, 0x407d08, 0x003d0040);
@@ -596,11 +577,11 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
        /* 8000+: per-TP state */
        for (i = 0; i < 10; i++) {
                if (units & (1<<i)) {
-                       if (dev_priv->chipset < 0xa0)
+                       if (device->chipset < 0xa0)
                                base = 0x408000 + (i<<12);
                        else
                                base = 0x408000 + (i<<11);
-                       if (dev_priv->chipset < 0xa0)
+                       if (device->chipset < 0xa0)
                                offset = base + 0xc00;
                        else
                                offset = base + 0x80;
@@ -609,9 +590,9 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
                        cp_ctx(ctx, offset + 0x08, 1);
 
                        /* per-MP state */
-                       for (j = 0; j < (dev_priv->chipset < 0xa0 ? 2 : 4); j++) {
+                       for (j = 0; j < (device->chipset < 0xa0 ? 2 : 4); j++) {
                                if (!(units & (1 << (j+24)))) continue;
-                               if (dev_priv->chipset < 0xa0)
+                               if (device->chipset < 0xa0)
                                        offset = base + 0x200 + (j<<7);
                                else
                                        offset = base + 0x100 + (j<<7);
@@ -620,7 +601,7 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
                                gr_def(ctx, offset + 0x04, 0x00160000);
                                gr_def(ctx, offset + 0x08, 0x01800000);
                                gr_def(ctx, offset + 0x18, 0x0003ffff);
-                               switch (dev_priv->chipset) {
+                               switch (device->chipset) {
                                case 0x50:
                                        gr_def(ctx, offset + 0x1c, 0x00080000);
                                        break;
@@ -651,53 +632,53 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
                                        break;
                                }
                                gr_def(ctx, offset + 0x40, 0x00010401);
-                               if (dev_priv->chipset == 0x50)
+                               if (device->chipset == 0x50)
                                        gr_def(ctx, offset + 0x48, 0x00000040);
                                else
                                        gr_def(ctx, offset + 0x48, 0x00000078);
                                gr_def(ctx, offset + 0x50, 0x000000bf);
                                gr_def(ctx, offset + 0x58, 0x00001210);
-                               if (dev_priv->chipset == 0x50)
+                               if (device->chipset == 0x50)
                                        gr_def(ctx, offset + 0x5c, 0x00000080);
                                else
                                        gr_def(ctx, offset + 0x5c, 0x08000080);
-                               if (dev_priv->chipset >= 0xa0)
+                               if (device->chipset >= 0xa0)
                                        gr_def(ctx, offset + 0x68, 0x0000003e);
                        }
 
-                       if (dev_priv->chipset < 0xa0)
+                       if (device->chipset < 0xa0)
                                cp_ctx(ctx, base + 0x300, 0x4);
                        else
                                cp_ctx(ctx, base + 0x300, 0x5);
-                       if (dev_priv->chipset == 0x50)
+                       if (device->chipset == 0x50)
                                gr_def(ctx, base + 0x304, 0x00007070);
-                       else if (dev_priv->chipset < 0xa0)
+                       else if (device->chipset < 0xa0)
                                gr_def(ctx, base + 0x304, 0x00027070);
-                       else if (!IS_NVA3F(dev_priv->chipset))
+                       else if (!IS_NVA3F(device->chipset))
                                gr_def(ctx, base + 0x304, 0x01127070);
                        else
                                gr_def(ctx, base + 0x304, 0x05127070);
 
-                       if (dev_priv->chipset < 0xa0)
+                       if (device->chipset < 0xa0)
                                cp_ctx(ctx, base + 0x318, 1);
                        else
                                cp_ctx(ctx, base + 0x320, 1);
-                       if (dev_priv->chipset == 0x50)
+                       if (device->chipset == 0x50)
                                gr_def(ctx, base + 0x318, 0x0003ffff);
-                       else if (dev_priv->chipset < 0xa0)
+                       else if (device->chipset < 0xa0)
                                gr_def(ctx, base + 0x318, 0x03ffffff);
                        else
                                gr_def(ctx, base + 0x320, 0x07ffffff);
 
-                       if (dev_priv->chipset < 0xa0)
+                       if (device->chipset < 0xa0)
                                cp_ctx(ctx, base + 0x324, 5);
                        else
                                cp_ctx(ctx, base + 0x328, 4);
 
-                       if (dev_priv->chipset < 0xa0) {
+                       if (device->chipset < 0xa0) {
                                cp_ctx(ctx, base + 0x340, 9);
                                offset = base + 0x340;
-                       } else if (!IS_NVA3F(dev_priv->chipset)) {
+                       } else if (!IS_NVA3F(device->chipset)) {
                                cp_ctx(ctx, base + 0x33c, 0xb);
                                offset = base + 0x344;
                        } else {
@@ -706,12 +687,12 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
                        }
                        gr_def(ctx, offset + 0x0, 0x00120407);
                        gr_def(ctx, offset + 0x4, 0x05091507);
-                       if (dev_priv->chipset == 0x84)
+                       if (device->chipset == 0x84)
                                gr_def(ctx, offset + 0x8, 0x05100202);
                        else
                                gr_def(ctx, offset + 0x8, 0x05010202);
                        gr_def(ctx, offset + 0xc, 0x00030201);
-                       if (dev_priv->chipset == 0xa3)
+                       if (device->chipset == 0xa3)
                                cp_ctx(ctx, base + 0x36c, 1);
 
                        cp_ctx(ctx, base + 0x400, 2);
@@ -720,7 +701,7 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
                        gr_def(ctx, base + 0x40c, 0x0d0c0b0a);
                        gr_def(ctx, base + 0x410, 0x00141210);
 
-                       if (dev_priv->chipset < 0xa0)
+                       if (device->chipset < 0xa0)
                                offset = base + 0x800;
                        else
                                offset = base + 0x500;
@@ -728,55 +709,55 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
                        gr_def(ctx, offset + 0x0, 0x000001f0);
                        gr_def(ctx, offset + 0x4, 0x00000001);
                        gr_def(ctx, offset + 0x8, 0x00000003);
-                       if (dev_priv->chipset == 0x50 || IS_NVAAF(dev_priv->chipset))
+                       if (device->chipset == 0x50 || IS_NVAAF(device->chipset))
                                gr_def(ctx, offset + 0xc, 0x00008000);
                        gr_def(ctx, offset + 0x14, 0x00039e00);
                        cp_ctx(ctx, offset + 0x1c, 2);
-                       if (dev_priv->chipset == 0x50)
+                       if (device->chipset == 0x50)
                                gr_def(ctx, offset + 0x1c, 0x00000040);
                        else
                                gr_def(ctx, offset + 0x1c, 0x00000100);
                        gr_def(ctx, offset + 0x20, 0x00003800);
 
-                       if (dev_priv->chipset >= 0xa0) {
+                       if (device->chipset >= 0xa0) {
                                cp_ctx(ctx, base + 0x54c, 2);
-                               if (!IS_NVA3F(dev_priv->chipset))
+                               if (!IS_NVA3F(device->chipset))
                                        gr_def(ctx, base + 0x54c, 0x003fe006);
                                else
                                        gr_def(ctx, base + 0x54c, 0x003fe007);
                                gr_def(ctx, base + 0x550, 0x003fe000);
                        }
 
-                       if (dev_priv->chipset < 0xa0)
+                       if (device->chipset < 0xa0)
                                offset = base + 0xa00;
                        else
                                offset = base + 0x680;
                        cp_ctx(ctx, offset, 1);
                        gr_def(ctx, offset, 0x00404040);
 
-                       if (dev_priv->chipset < 0xa0)
+                       if (device->chipset < 0xa0)
                                offset = base + 0xe00;
                        else
                                offset = base + 0x700;
                        cp_ctx(ctx, offset, 2);
-                       if (dev_priv->chipset < 0xa0)
+                       if (device->chipset < 0xa0)
                                gr_def(ctx, offset, 0x0077f005);
-                       else if (dev_priv->chipset == 0xa5)
+                       else if (device->chipset == 0xa5)
                                gr_def(ctx, offset, 0x6cf7f007);
-                       else if (dev_priv->chipset == 0xa8)
+                       else if (device->chipset == 0xa8)
                                gr_def(ctx, offset, 0x6cfff007);
-                       else if (dev_priv->chipset == 0xac)
+                       else if (device->chipset == 0xac)
                                gr_def(ctx, offset, 0x0cfff007);
                        else
                                gr_def(ctx, offset, 0x0cf7f007);
-                       if (dev_priv->chipset == 0x50)
+                       if (device->chipset == 0x50)
                                gr_def(ctx, offset + 0x4, 0x00007fff);
-                       else if (dev_priv->chipset < 0xa0)
+                       else if (device->chipset < 0xa0)
                                gr_def(ctx, offset + 0x4, 0x003f7fff);
                        else
                                gr_def(ctx, offset + 0x4, 0x02bf7fff);
                        cp_ctx(ctx, offset + 0x2c, 1);
-                       if (dev_priv->chipset == 0x50) {
+                       if (device->chipset == 0x50) {
                                cp_ctx(ctx, offset + 0x50, 9);
                                gr_def(ctx, offset + 0x54, 0x000003ff);
                                gr_def(ctx, offset + 0x58, 0x00000003);
@@ -785,7 +766,7 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
                                gr_def(ctx, offset + 0x64, 0x0000001f);
                                gr_def(ctx, offset + 0x68, 0x0000000f);
                                gr_def(ctx, offset + 0x6c, 0x0000000f);
-                       } else if (dev_priv->chipset < 0xa0) {
+                       } else if (device->chipset < 0xa0) {
                                cp_ctx(ctx, offset + 0x50, 1);
                                cp_ctx(ctx, offset + 0x70, 1);
                        } else {
@@ -797,7 +778,7 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
 }
 
 static void
-dd_emit(struct nouveau_grctx *ctx, int num, uint32_t val) {
+dd_emit(struct nouveau_grctx *ctx, int num, u32 val) {
        int i;
        if (val && ctx->mode == NOUVEAU_GRCTX_VALS)
                for (i = 0; i < num; i++)
@@ -808,7 +789,7 @@ dd_emit(struct nouveau_grctx *ctx, int num, uint32_t val) {
 static void
 nv50_graph_construct_mmio_ddata(struct nouveau_grctx *ctx)
 {
-       struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
+       struct nouveau_device *device = ctx->device;
        int base, num;
        base = ctx->ctxvals_pos;
 
@@ -822,7 +803,7 @@ nv50_graph_construct_mmio_ddata(struct nouveau_grctx *ctx)
        dd_emit(ctx, 1, 1);     /* 00000001 SRC_LINEAR #1 */
        dd_emit(ctx, 1, 0);     /* 000000ff SRC_ADDRESS_HIGH */
        dd_emit(ctx, 1, 0);     /* 00000001 SRC_SRGB */
-       if (dev_priv->chipset >= 0x94)
+       if (device->chipset >= 0x94)
                dd_emit(ctx, 1, 0);     /* 00000003 eng2d UNK0258 */
        dd_emit(ctx, 1, 1);     /* 00000fff SRC_DEPTH */
        dd_emit(ctx, 1, 0x100); /* 0000ffff SRC_HEIGHT */
@@ -851,7 +832,7 @@ nv50_graph_construct_mmio_ddata(struct nouveau_grctx *ctx)
        dd_emit(ctx, 1, 1);             /* 0000007f BLOCKDIM_Z */
        dd_emit(ctx, 1, 4);             /* 000000ff CP_REG_ALLOC_TEMP */
        dd_emit(ctx, 1, 1);             /* 00000001 BLOCKDIM_DIRTY */
-       if (IS_NVA3F(dev_priv->chipset))
+       if (IS_NVA3F(device->chipset))
                dd_emit(ctx, 1, 0);     /* 00000003 UNK03E8 */
        dd_emit(ctx, 1, 1);             /* 0000007f BLOCK_ALLOC_HALFWARPS */
        dd_emit(ctx, 1, 1);             /* 00000007 LOCAL_WARPS_NO_CLAMP */
@@ -863,7 +844,7 @@ nv50_graph_construct_mmio_ddata(struct nouveau_grctx *ctx)
        dd_emit(ctx, 1, 1);             /* 000007ff BLOCK_ALLOC_THREADS */
 
        /* compat 2d state */
-       if (dev_priv->chipset == 0x50) {
+       if (device->chipset == 0x50) {
                dd_emit(ctx, 4, 0);             /* 0000ffff clip X, Y, W, H */
 
                dd_emit(ctx, 1, 1);             /* ffffffff chroma COLOR_FORMAT */
@@ -923,7 +904,7 @@ nv50_graph_construct_mmio_ddata(struct nouveau_grctx *ctx)
        dd_emit(ctx, 1, 0x100);         /* ffffffff m2mf TILING_PITCH_IN */
 
        /* more compat 2d state */
-       if (dev_priv->chipset == 0x50) {
+       if (device->chipset == 0x50) {
                dd_emit(ctx, 1, 1);             /* ffffffff line COLOR_FORMAT */
                dd_emit(ctx, 1, 0);             /* ffffffff line OPERATION */
 
@@ -957,18 +938,18 @@ nv50_graph_construct_mmio_ddata(struct nouveau_grctx *ctx)
        dd_emit(ctx, 1, 0);             /* 000000ff UNK12B0_2 */
        dd_emit(ctx, 1, 0);             /* 0000000f FP_TEXTURES_LOG2 */
        dd_emit(ctx, 1, 0);             /* 0000000f FP_SAMPLERS_LOG2 */
-       if (IS_NVA3F(dev_priv->chipset)) {
+       if (IS_NVA3F(device->chipset)) {
                dd_emit(ctx, 1, 0);     /* ffffffff */
                dd_emit(ctx, 1, 0);     /* 0000007f MULTISAMPLE_SAMPLES_LOG2 */
        } else {
                dd_emit(ctx, 1, 0);     /* 0000000f MULTISAMPLE_SAMPLES_LOG2 */
        }
        dd_emit(ctx, 1, 0xc);           /* 000000ff SEMANTIC_COLOR.BFC0_ID */
-       if (dev_priv->chipset != 0x50)
+       if (device->chipset != 0x50)
                dd_emit(ctx, 1, 0);     /* 00000001 SEMANTIC_COLOR.CLMP_EN */
        dd_emit(ctx, 1, 8);             /* 000000ff SEMANTIC_COLOR.COLR_NR */
        dd_emit(ctx, 1, 0x14);          /* 000000ff SEMANTIC_COLOR.FFC0_ID */
-       if (dev_priv->chipset == 0x50) {
+       if (device->chipset == 0x50) {
                dd_emit(ctx, 1, 0);     /* 000000ff SEMANTIC_LAYER */
                dd_emit(ctx, 1, 0);     /* 00000001 */
        } else {
@@ -994,7 +975,7 @@ nv50_graph_construct_mmio_ddata(struct nouveau_grctx *ctx)
        dd_emit(ctx, 8, 0);             /* ffffffff RT_ADDRESS_LOW */
        dd_emit(ctx, 1, 0xcf);          /* 000000ff RT_FORMAT */
        dd_emit(ctx, 7, 0);             /* 000000ff RT_FORMAT */
-       if (dev_priv->chipset != 0x50)
+       if (device->chipset != 0x50)
                dd_emit(ctx, 3, 0);     /* 1, 1, 1 */
        else
                dd_emit(ctx, 2, 0);     /* 1, 1 */
@@ -1002,15 +983,15 @@ nv50_graph_construct_mmio_ddata(struct nouveau_grctx *ctx)
        dd_emit(ctx, 1, 0x80);          /* 0000ffff GP_VERTEX_OUTPUT_COUNT*/
        dd_emit(ctx, 1, 4);             /* 000000ff GP_REG_ALLOC_RESULT */
        dd_emit(ctx, 1, 4);             /* 000000ff GP_RESULT_MAP_SIZE */
-       if (IS_NVA3F(dev_priv->chipset)) {
+       if (IS_NVA3F(device->chipset)) {
                dd_emit(ctx, 1, 3);     /* 00000003 */
                dd_emit(ctx, 1, 0);     /* 00000001 UNK1418. Alone. */
        }
-       if (dev_priv->chipset != 0x50)
+       if (device->chipset != 0x50)
                dd_emit(ctx, 1, 3);     /* 00000003 UNK15AC */
        dd_emit(ctx, 1, 1);             /* ffffffff RASTERIZE_ENABLE */
        dd_emit(ctx, 1, 0);             /* 00000001 FP_CONTROL.EXPORTS_Z */
-       if (dev_priv->chipset != 0x50)
+       if (device->chipset != 0x50)
                dd_emit(ctx, 1, 0);     /* 00000001 FP_CONTROL.MULTIPLE_RESULTS */
        dd_emit(ctx, 1, 0x12);          /* 000000ff FP_INTERPOLANT_CTRL.COUNT */
        dd_emit(ctx, 1, 0x10);          /* 000000ff FP_INTERPOLANT_CTRL.COUNT_NONFLAT */
@@ -1022,16 +1003,16 @@ nv50_graph_construct_mmio_ddata(struct nouveau_grctx *ctx)
        dd_emit(ctx, 1, 4);             /* 000000ff FP_RESULT_COUNT */
        dd_emit(ctx, 1, 2);             /* ffffffff REG_MODE */
        dd_emit(ctx, 1, 4);             /* 000000ff FP_REG_ALLOC_TEMP */
-       if (dev_priv->chipset >= 0xa0)
+       if (device->chipset >= 0xa0)
                dd_emit(ctx, 1, 0);     /* ffffffff */
        dd_emit(ctx, 1, 0);             /* 00000001 GP_BUILTIN_RESULT_EN.LAYER_IDX */
        dd_emit(ctx, 1, 0);             /* ffffffff STRMOUT_ENABLE */
        dd_emit(ctx, 1, 0x3fffff);      /* 003fffff TIC_LIMIT */
        dd_emit(ctx, 1, 0x1fff);        /* 000fffff TSC_LIMIT */
        dd_emit(ctx, 1, 0);             /* 00000001 VERTEX_TWO_SIDE_ENABLE*/
-       if (dev_priv->chipset != 0x50)
+       if (device->chipset != 0x50)
                dd_emit(ctx, 8, 0);     /* 00000001 */
-       if (dev_priv->chipset >= 0xa0) {
+       if (device->chipset >= 0xa0) {
                dd_emit(ctx, 1, 1);     /* 00000007 VTX_ATTR_DEFINE.COMP */
                dd_emit(ctx, 1, 1);     /* 00000007 VTX_ATTR_DEFINE.SIZE */
                dd_emit(ctx, 1, 2);     /* 00000007 VTX_ATTR_DEFINE.TYPE */
@@ -1042,20 +1023,20 @@ nv50_graph_construct_mmio_ddata(struct nouveau_grctx *ctx)
        dd_emit(ctx, 1, 1);             /* 00000001 ZETA_ENABLE */
        dd_emit(ctx, 1, 0);             /* 0000000f VP_TEXTURES_LOG2 */
        dd_emit(ctx, 1, 0);             /* 0000000f VP_SAMPLERS_LOG2 */
-       if (IS_NVA3F(dev_priv->chipset))
+       if (IS_NVA3F(device->chipset))
                dd_emit(ctx, 1, 0);     /* 00000001 */
        dd_emit(ctx, 1, 2);             /* 00000003 POLYGON_MODE_BACK */
-       if (dev_priv->chipset >= 0xa0)
+       if (device->chipset >= 0xa0)
                dd_emit(ctx, 1, 0);     /* 00000003 VTX_ATTR_DEFINE.SIZE - 1 */
        dd_emit(ctx, 1, 0);             /* 0000ffff CB_ADDR_INDEX */
-       if (dev_priv->chipset >= 0xa0)
+       if (device->chipset >= 0xa0)
                dd_emit(ctx, 1, 0);     /* 00000003 */
        dd_emit(ctx, 1, 0);             /* 00000001 CULL_FACE_ENABLE */
        dd_emit(ctx, 1, 1);             /* 00000003 CULL_FACE */
        dd_emit(ctx, 1, 0);             /* 00000001 FRONT_FACE */
        dd_emit(ctx, 1, 2);             /* 00000003 POLYGON_MODE_FRONT */
        dd_emit(ctx, 1, 0x1000);        /* 00007fff UNK141C */
-       if (dev_priv->chipset != 0x50) {
+       if (device->chipset != 0x50) {
                dd_emit(ctx, 1, 0xe00);         /* 7fff */
                dd_emit(ctx, 1, 0x1000);        /* 7fff */
                dd_emit(ctx, 1, 0x1e00);        /* 7fff */
@@ -1070,10 +1051,10 @@ nv50_graph_construct_mmio_ddata(struct nouveau_grctx *ctx)
        dd_emit(ctx, 1, 0);             /* 00000001 VTX_ATTR_MASK_UNK0 nonempty */
        dd_emit(ctx, 1, 0);             /* 00000001 VTX_ATTR_MASK_UNK1 nonempty */
        dd_emit(ctx, 1, 0x200);         /* 0003ffff GP_VERTEX_OUTPUT_COUNT*GP_REG_ALLOC_RESULT */
-       if (IS_NVA3F(dev_priv->chipset))
+       if (IS_NVA3F(device->chipset))
                dd_emit(ctx, 1, 0x200);
        dd_emit(ctx, 1, 0);             /* 00000001 */
-       if (dev_priv->chipset < 0xa0) {
+       if (device->chipset < 0xa0) {
                dd_emit(ctx, 1, 1);     /* 00000001 */
                dd_emit(ctx, 1, 0x70);  /* 000000ff */
                dd_emit(ctx, 1, 0x80);  /* 000000ff */
@@ -1120,7 +1101,7 @@ nv50_graph_construct_mmio_ddata(struct nouveau_grctx *ctx)
 
        num = ctx->ctxvals_pos - base;
        ctx->ctxvals_pos = base;
-       if (IS_NVA3F(dev_priv->chipset))
+       if (IS_NVA3F(device->chipset))
                cp_ctx(ctx, 0x404800, num);
        else
                cp_ctx(ctx, 0x405400, num);
@@ -1169,7 +1150,7 @@ nv50_graph_construct_mmio_ddata(struct nouveau_grctx *ctx)
  */
 
 static void
-xf_emit(struct nouveau_grctx *ctx, int num, uint32_t val) {
+xf_emit(struct nouveau_grctx *ctx, int num, u32 val) {
        int i;
        if (val && ctx->mode == NOUVEAU_GRCTX_VALS)
                for (i = 0; i < num; i++)
@@ -1201,16 +1182,16 @@ static void nv50_graph_construct_xfer_tp(struct nouveau_grctx *ctx);
 static void
 nv50_graph_construct_xfer1(struct nouveau_grctx *ctx)
 {
-       struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
+       struct nouveau_device *device = ctx->device;
        int i;
        int offset;
        int size = 0;
-       uint32_t units = nv_rd32 (ctx->dev, 0x1540);
+       u32 units = nv_rd32 (ctx->device, 0x1540);
 
        offset = (ctx->ctxvals_pos+0x3f)&~0x3f;
        ctx->ctxvals_base = offset;
 
-       if (dev_priv->chipset < 0xa0) {
+       if (device->chipset < 0xa0) {
                /* Strand 0 */
                ctx->ctxvals_pos = offset;
                nv50_graph_construct_gene_dispatch(ctx);
@@ -1280,7 +1261,7 @@ nv50_graph_construct_xfer1(struct nouveau_grctx *ctx)
 
                /* Strand 2 */
                ctx->ctxvals_pos = offset + 2;
-               if (dev_priv->chipset == 0xa0)
+               if (device->chipset == 0xa0)
                        nv50_graph_construct_gene_unk14xx(ctx);
                nv50_graph_construct_gene_unk24xx(ctx);
                if ((ctx->ctxvals_pos-offset)/8 > size)
@@ -1327,7 +1308,7 @@ nv50_graph_construct_xfer1(struct nouveau_grctx *ctx)
 
                /* Strand 7 */
                ctx->ctxvals_pos = offset + 7;
-               if (dev_priv->chipset == 0xa0) {
+               if (device->chipset == 0xa0) {
                        if (units & (1 << 4))
                                nv50_graph_construct_xfer_tp(ctx);
                        if (units & (1 << 5))
@@ -1365,24 +1346,24 @@ static void
 nv50_graph_construct_gene_dispatch(struct nouveau_grctx *ctx)
 {
        /* start of strand 0 */
-       struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
+       struct nouveau_device *device = ctx->device;
        /* SEEK */
-       if (dev_priv->chipset == 0x50)
+       if (device->chipset == 0x50)
                xf_emit(ctx, 5, 0);
-       else if (!IS_NVA3F(dev_priv->chipset))
+       else if (!IS_NVA3F(device->chipset))
                xf_emit(ctx, 6, 0);
        else
                xf_emit(ctx, 4, 0);
        /* SEEK */
        /* the PGRAPH's internal FIFO */
-       if (dev_priv->chipset == 0x50)
+       if (device->chipset == 0x50)
                xf_emit(ctx, 8*3, 0);
        else
                xf_emit(ctx, 0x100*3, 0);
        /* and another bonus slot?!? */
        xf_emit(ctx, 3, 0);
        /* and YET ANOTHER bonus slot? */
-       if (IS_NVA3F(dev_priv->chipset))
+       if (IS_NVA3F(device->chipset))
                xf_emit(ctx, 3, 0);
        /* SEEK */
        /* CTX_SWITCH: caches of gr objects bound to subchannels. 8 values, last used index */
@@ -1394,7 +1375,7 @@ nv50_graph_construct_gene_dispatch(struct nouveau_grctx *ctx)
        /* SEEK */
        xf_emit(ctx, 9, 0);
        /* SEEK */
-       if (dev_priv->chipset < 0x90)
+       if (device->chipset < 0x90)
                xf_emit(ctx, 4, 0);
        /* SEEK */
        xf_emit(ctx, 2, 0);
@@ -1407,9 +1388,9 @@ nv50_graph_construct_gene_dispatch(struct nouveau_grctx *ctx)
        xf_emit(ctx, 6*2, 0);
        xf_emit(ctx, 2, 0);
        /* SEEK */
-       if (dev_priv->chipset == 0x50)
+       if (device->chipset == 0x50)
                xf_emit(ctx, 0x1c, 0);
-       else if (dev_priv->chipset < 0xa0)
+       else if (device->chipset < 0xa0)
                xf_emit(ctx, 0x1e, 0);
        else
                xf_emit(ctx, 0x22, 0);
@@ -1421,9 +1402,9 @@ static void
 nv50_graph_construct_gene_m2mf(struct nouveau_grctx *ctx)
 {
        /* Strand 0, right after dispatch */
-       struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
+       struct nouveau_device *device = ctx->device;
        int smallm2mf = 0;
-       if (dev_priv->chipset < 0x92 || dev_priv->chipset == 0x98)
+       if (device->chipset < 0x92 || device->chipset == 0x98)
                smallm2mf = 1;
        /* SEEK */
        xf_emit (ctx, 1, 0);            /* DMA_NOTIFY instance >> 4 */
@@ -1472,10 +1453,10 @@ nv50_graph_construct_gene_m2mf(struct nouveau_grctx *ctx)
 static void
 nv50_graph_construct_gene_ccache(struct nouveau_grctx *ctx)
 {
-       struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
+       struct nouveau_device *device = ctx->device;
        xf_emit(ctx, 2, 0);             /* RO */
        xf_emit(ctx, 0x800, 0);         /* ffffffff */
-       switch (dev_priv->chipset) {
+       switch (device->chipset) {
        case 0x50:
        case 0x92:
        case 0xa0:
@@ -1540,7 +1521,7 @@ nv50_graph_construct_gene_ccache(struct nouveau_grctx *ctx)
 static void
 nv50_graph_construct_gene_unk10xx(struct nouveau_grctx *ctx)
 {
-       struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
+       struct nouveau_device *device = ctx->device;
        int i;
        /* end of area 2 on pre-NVA0, area 1 on NVAx */
        xf_emit(ctx, 1, 4);             /* 000000ff GP_RESULT_MAP_SIZE */
@@ -1550,14 +1531,14 @@ nv50_graph_construct_gene_unk10xx(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 4);             /* 000000ff GP_REG_ALLOC_RESULT */
        xf_emit(ctx, 1, 0x80c14);       /* 01ffffff SEMANTIC_COLOR */
        xf_emit(ctx, 1, 0);             /* 00000001 VERTEX_TWO_SIDE_ENABLE */
-       if (dev_priv->chipset == 0x50)
+       if (device->chipset == 0x50)
                xf_emit(ctx, 1, 0x3ff);
        else
                xf_emit(ctx, 1, 0x7ff); /* 000007ff */
        xf_emit(ctx, 1, 0);             /* 111/113 */
        xf_emit(ctx, 1, 0);             /* ffffffff tesla UNK1A30 */
        for (i = 0; i < 8; i++) {
-               switch (dev_priv->chipset) {
+               switch (device->chipset) {
                case 0x50:
                case 0x86:
                case 0x98:
@@ -1600,7 +1581,7 @@ nv50_graph_construct_gene_unk10xx(struct nouveau_grctx *ctx)
 static void
 nv50_graph_construct_gene_unk34xx(struct nouveau_grctx *ctx)
 {
-       struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
+       struct nouveau_device *device = ctx->device;
        /* end of area 2 on pre-NVA0, area 1 on NVAx */
        xf_emit(ctx, 1, 0);             /* 00000001 VIEWPORT_CLIP_RECTS_EN */
        xf_emit(ctx, 1, 0);             /* 00000003 VIEWPORT_CLIP_MODE */
@@ -1614,9 +1595,9 @@ nv50_graph_construct_gene_unk34xx(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 0);             /* 00000003 WINDOW_ORIGIN */
        xf_emit(ctx, 1, 0);             /* 00000007 */
        xf_emit(ctx, 1, 0x1fe21);       /* 0001ffff tesla UNK0FAC */
-       if (dev_priv->chipset >= 0xa0)
+       if (device->chipset >= 0xa0)
                xf_emit(ctx, 1, 0x0fac6881);
-       if (IS_NVA3F(dev_priv->chipset)) {
+       if (IS_NVA3F(device->chipset)) {
                xf_emit(ctx, 1, 1);
                xf_emit(ctx, 3, 0);
        }
@@ -1625,9 +1606,9 @@ nv50_graph_construct_gene_unk34xx(struct nouveau_grctx *ctx)
 static void
 nv50_graph_construct_gene_unk14xx(struct nouveau_grctx *ctx)
 {
-       struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
+       struct nouveau_device *device = ctx->device;
        /* middle of area 2 on pre-NVA0, beginning of area 2 on NVA0, area 7 on >NVA0 */
-       if (dev_priv->chipset != 0x50) {
+       if (device->chipset != 0x50) {
                xf_emit(ctx, 5, 0);             /* ffffffff */
                xf_emit(ctx, 1, 0x80c14);       /* 01ffffff SEMANTIC_COLOR */
                xf_emit(ctx, 1, 0);             /* 00000001 */
@@ -1643,14 +1624,14 @@ nv50_graph_construct_gene_unk14xx(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 0);                     /* 00000001 GP_ENABLE */
        xf_emit(ctx, 1, 0x10);                  /* 7f/ff VIEW_VOLUME_CLIP_CTRL */
        xf_emit(ctx, 1, 0);                     /* 000000ff VP_CLIP_DISTANCE_ENABLE */
-       if (dev_priv->chipset != 0x50)
+       if (device->chipset != 0x50)
                xf_emit(ctx, 1, 0);             /* 3ff */
        xf_emit(ctx, 1, 0);                     /* 000000ff tesla UNK1940 */
        xf_emit(ctx, 1, 0);                     /* 00000001 tesla UNK0D7C */
        xf_emit(ctx, 1, 0x804);                 /* 00000fff SEMANTIC_CLIP */
        xf_emit(ctx, 1, 1);                     /* 00000001 VIEWPORT_TRANSFORM_EN */
        xf_emit(ctx, 1, 0x1a);                  /* 0000001f POLYGON_MODE */
-       if (dev_priv->chipset != 0x50)
+       if (device->chipset != 0x50)
                xf_emit(ctx, 1, 0x7f);          /* 000000ff tesla UNK0FFC */
        xf_emit(ctx, 1, 0);                     /* ffffffff tesla UNK1A30 */
        xf_emit(ctx, 1, 1);                     /* 00000001 SHADE_MODEL */
@@ -1669,7 +1650,7 @@ nv50_graph_construct_gene_unk14xx(struct nouveau_grctx *ctx)
        xf_emit(ctx, 4, 0);                     /* ffffffff NOPERSPECTIVE_BITMAP */
        xf_emit(ctx, 1, 0);                     /* 00000001 tesla UNK1900 */
        xf_emit(ctx, 1, 0);                     /* 0000000f */
-       if (dev_priv->chipset == 0x50)
+       if (device->chipset == 0x50)
                xf_emit(ctx, 1, 0x3ff);         /* 000003ff tesla UNK0D68 */
        else
                xf_emit(ctx, 1, 0x7ff);         /* 000007ff tesla UNK0D68 */
@@ -1704,11 +1685,11 @@ nv50_graph_construct_gene_unk14xx(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 0);                     /* 00000001 LINE_STIPPLE_ENABLE */
        xf_emit(ctx, 1, 0);                     /* 00000001 LINE_SMOOTH_ENABLE */
        xf_emit(ctx, 1, 0);                     /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */
-       if (IS_NVA3F(dev_priv->chipset))
+       if (IS_NVA3F(device->chipset))
                xf_emit(ctx, 1, 0);             /* 00000001 */
        xf_emit(ctx, 1, 0x1a);                  /* 0000001f POLYGON_MODE */
        xf_emit(ctx, 1, 0x10);                  /* 000000ff VIEW_VOLUME_CLIP_CTRL */
-       if (dev_priv->chipset != 0x50) {
+       if (device->chipset != 0x50) {
                xf_emit(ctx, 1, 0);             /* ffffffff */
                xf_emit(ctx, 1, 0);             /* 00000001 */
                xf_emit(ctx, 1, 0);             /* 000003ff */
@@ -1736,7 +1717,7 @@ nv50_graph_construct_gene_unk14xx(struct nouveau_grctx *ctx)
 static void
 nv50_graph_construct_gene_zcull(struct nouveau_grctx *ctx)
 {
-       struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
+       struct nouveau_device *device = ctx->device;
        /* end of strand 0 on pre-NVA0, beginning of strand 6 on NVAx */
        /* SEEK */
        xf_emit(ctx, 1, 0x3f);          /* 0000003f UNK1590 */
@@ -1774,7 +1755,7 @@ nv50_graph_construct_gene_zcull(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 0);             /* 00000001 STENCIL_BACK_ENABLE */
        xf_emit(ctx, 1, 0);             /* ffffffff CLEAR_DEPTH */
        xf_emit(ctx, 1, 0);             /* 00000007 */
-       if (dev_priv->chipset != 0x50)
+       if (device->chipset != 0x50)
                xf_emit(ctx, 1, 0);     /* 00000003 tesla UNK1108 */
        xf_emit(ctx, 1, 0);             /* 00000001 SAMPLECNT_ENABLE */
        xf_emit(ctx, 1, 0);             /* 0000000f ZETA_FORMAT */
@@ -1789,7 +1770,7 @@ nv50_graph_construct_gene_zcull(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 0);             /* 00000001 VIEWPORT_CLIP_RECTS_EN */
        xf_emit(ctx, 1, 3);             /* 00000003 FP_CTRL_UNK196C */
        xf_emit(ctx, 1, 0);             /* 00000003 tesla UNK1968 */
-       if (dev_priv->chipset != 0x50)
+       if (device->chipset != 0x50)
                xf_emit(ctx, 1, 0);     /* 0fffffff tesla UNK1104 */
        xf_emit(ctx, 1, 0);             /* 00000001 tesla UNK151C */
 }
@@ -1817,7 +1798,7 @@ nv50_graph_construct_gene_clipid(struct nouveau_grctx *ctx)
 static void
 nv50_graph_construct_gene_unk24xx(struct nouveau_grctx *ctx)
 {
-       struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
+       struct nouveau_device *device = ctx->device;
        int i;
        /* middle of strand 0 on pre-NVA0 [after m2mf], end of strand 2 on NVAx */
        /* SEEK */
@@ -1829,7 +1810,7 @@ nv50_graph_construct_gene_unk24xx(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 4);             /* 0000007f VP_RESULT_MAP_SIZE */
        xf_emit(ctx, 1, 4);             /* 000000ff GP_RESULT_MAP_SIZE */
        /* SEEK */
-       if (IS_NVA3F(dev_priv->chipset)) {
+       if (IS_NVA3F(device->chipset)) {
                xf_emit(ctx, 4, 0);     /* RO */
                xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */
                xf_emit(ctx, 1, 0);     /* 1ff */
@@ -1860,7 +1841,7 @@ nv50_graph_construct_gene_unk24xx(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 4);             /* 000000ff GP_RESULT_MAP_SIZE */
        xf_emit(ctx, 1, 4);             /* 0000007f VP_RESULT_MAP_SIZE */
        xf_emit(ctx, 1, 0x8100c12);     /* 1fffffff FP_INTERPOLANT_CTRL */
-       if (dev_priv->chipset != 0x50)
+       if (device->chipset != 0x50)
                xf_emit(ctx, 1, 3);     /* 00000003 tesla UNK1100 */
        /* SEEK */
        xf_emit(ctx, 1, 0);             /* 00000001 GP_ENABLE */
@@ -1869,7 +1850,7 @@ nv50_graph_construct_gene_unk24xx(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 0x80c14);       /* 01ffffff SEMANTIC_COLOR */
        xf_emit(ctx, 1, 1);             /* 00000001 */
        /* SEEK */
-       if (dev_priv->chipset >= 0xa0)
+       if (device->chipset >= 0xa0)
                xf_emit(ctx, 2, 4);     /* 000000ff */
        xf_emit(ctx, 1, 0x80c14);       /* 01ffffff SEMANTIC_COLOR */
        xf_emit(ctx, 1, 0);             /* 00000001 VERTEX_TWO_SIDE_ENABLE */
@@ -1893,20 +1874,20 @@ nv50_graph_construct_gene_unk24xx(struct nouveau_grctx *ctx)
        xf_emit(ctx, 0x10, 0);          /* 00ffffff POINT_COORD_REPLACE_MAP */
        xf_emit(ctx, 1, 0);             /* 00000003 WINDOW_ORIGIN */
        xf_emit(ctx, 1, 0x8100c12);     /* 1fffffff FP_INTERPOLANT_CTRL */
-       if (dev_priv->chipset != 0x50)
+       if (device->chipset != 0x50)
                xf_emit(ctx, 1, 0);     /* 000003ff */
 }
 
 static void
 nv50_graph_construct_gene_vfetch(struct nouveau_grctx *ctx)
 {
-       struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
+       struct nouveau_device *device = ctx->device;
        int acnt = 0x10, rep, i;
        /* beginning of strand 1 on pre-NVA0, strand 3 on NVAx */
-       if (IS_NVA3F(dev_priv->chipset))
+       if (IS_NVA3F(device->chipset))
                acnt = 0x20;
        /* SEEK */
-       if (dev_priv->chipset >= 0xa0) {
+       if (device->chipset >= 0xa0) {
                xf_emit(ctx, 1, 0);     /* ffffffff tesla UNK13A4 */
                xf_emit(ctx, 1, 1);     /* 00000fff tesla UNK1318 */
        }
@@ -1923,9 +1904,9 @@ nv50_graph_construct_gene_vfetch(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 0);             /* 0000ffff turing USER_PARAM_COUNT */
        xf_emit(ctx, 1, 0);             /* ffffffff tesla UNK1A30 */
        /* SEEK */
-       if (IS_NVA3F(dev_priv->chipset))
+       if (IS_NVA3F(device->chipset))
                xf_emit(ctx, 0xb, 0);   /* RO */
-       else if (dev_priv->chipset >= 0xa0)
+       else if (device->chipset >= 0xa0)
                xf_emit(ctx, 0x9, 0);   /* RO */
        else
                xf_emit(ctx, 0x8, 0);   /* RO */
@@ -1944,11 +1925,11 @@ nv50_graph_construct_gene_vfetch(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 4);             /* 000001ff UNK1A28 */
        xf_emit(ctx, 1, 8);             /* 000001ff UNK0DF0 */
        xf_emit(ctx, 1, 0);             /* 00000001 GP_ENABLE */
-       if (dev_priv->chipset == 0x50)
+       if (device->chipset == 0x50)
                xf_emit(ctx, 1, 0x3ff); /* 3ff tesla UNK0D68 */
        else
                xf_emit(ctx, 1, 0x7ff); /* 7ff tesla UNK0D68 */
-       if (dev_priv->chipset == 0xa8)
+       if (device->chipset == 0xa8)
                xf_emit(ctx, 1, 0x1e00);        /* 7fff */
        /* SEEK */
        xf_emit(ctx, 0xc, 0);           /* RO or close */
@@ -1956,13 +1937,13 @@ nv50_graph_construct_gene_vfetch(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 0xf);           /* ffffffff VP_ATTR_EN */
        xf_emit(ctx, (acnt/8)-1, 0);    /* ffffffff VP_ATTR_EN */
        xf_emit(ctx, 1, 0);             /* 0000000f VP_GP_BUILTIN_ATTR_EN */
-       if (dev_priv->chipset > 0x50 && dev_priv->chipset < 0xa0)
+       if (device->chipset > 0x50 && device->chipset < 0xa0)
                xf_emit(ctx, 2, 0);     /* ffffffff */
        else
                xf_emit(ctx, 1, 0);     /* ffffffff */
        xf_emit(ctx, 1, 0);             /* 00000003 tesla UNK0FD8 */
        /* SEEK */
-       if (IS_NVA3F(dev_priv->chipset)) {
+       if (IS_NVA3F(device->chipset)) {
                xf_emit(ctx, 0x10, 0);  /* 0? */
                xf_emit(ctx, 2, 0);     /* weird... */
                xf_emit(ctx, 2, 0);     /* RO */
@@ -1975,7 +1956,7 @@ nv50_graph_construct_gene_vfetch(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 0);             /* ffffffff VB_ELEMENT_BASE */
        xf_emit(ctx, 1, 0);             /* ffffffff UNK1438 */
        xf_emit(ctx, acnt, 0);          /* 1 tesla UNK1000 */
-       if (dev_priv->chipset >= 0xa0)
+       if (device->chipset >= 0xa0)
                xf_emit(ctx, 1, 0);     /* ffffffff tesla UNK1118? */
        /* SEEK */
        xf_emit(ctx, acnt, 0);          /* ffffffff VERTEX_ARRAY_UNK90C */
@@ -2013,23 +1994,23 @@ nv50_graph_construct_gene_vfetch(struct nouveau_grctx *ctx)
        xf_emit(ctx, acnt, 0);          /* 000000ff VERTEX_LIMIT_HIGH */
        xf_emit(ctx, 3, 0);             /* f/1f */
        /* SEEK */
-       if (IS_NVA3F(dev_priv->chipset)) {
+       if (IS_NVA3F(device->chipset)) {
                xf_emit(ctx, acnt, 0);          /* f */
                xf_emit(ctx, 3, 0);             /* f/1f */
        }
        /* SEEK */
-       if (IS_NVA3F(dev_priv->chipset))
+       if (IS_NVA3F(device->chipset))
                xf_emit(ctx, 2, 0);     /* RO */
        else
                xf_emit(ctx, 5, 0);     /* RO */
        /* SEEK */
        xf_emit(ctx, 1, 0);             /* ffff DMA_VTXBUF */
        /* SEEK */
-       if (dev_priv->chipset < 0xa0) {
+       if (device->chipset < 0xa0) {
                xf_emit(ctx, 0x41, 0);  /* RO */
                /* SEEK */
                xf_emit(ctx, 0x11, 0);  /* RO */
-       } else if (!IS_NVA3F(dev_priv->chipset))
+       } else if (!IS_NVA3F(device->chipset))
                xf_emit(ctx, 0x50, 0);  /* RO */
        else
                xf_emit(ctx, 0x58, 0);  /* RO */
@@ -2041,7 +2022,7 @@ nv50_graph_construct_gene_vfetch(struct nouveau_grctx *ctx)
        xf_emit(ctx, acnt*4, 0);        /* ffffffff VTX_ATTR */
        xf_emit(ctx, 4, 0);             /* f/1f, 0, 0, 0 */
        /* SEEK */
-       if (IS_NVA3F(dev_priv->chipset))
+       if (IS_NVA3F(device->chipset))
                xf_emit(ctx, 0x1d, 0);  /* RO */
        else
                xf_emit(ctx, 0x16, 0);  /* RO */
@@ -2049,21 +2030,21 @@ nv50_graph_construct_gene_vfetch(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 0xf);           /* ffffffff VP_ATTR_EN */
        xf_emit(ctx, (acnt/8)-1, 0);    /* ffffffff VP_ATTR_EN */
        /* SEEK */
-       if (dev_priv->chipset < 0xa0)
+       if (device->chipset < 0xa0)
                xf_emit(ctx, 8, 0);     /* RO */
-       else if (IS_NVA3F(dev_priv->chipset))
+       else if (IS_NVA3F(device->chipset))
                xf_emit(ctx, 0xc, 0);   /* RO */
        else
                xf_emit(ctx, 7, 0);     /* RO */
        /* SEEK */
        xf_emit(ctx, 0xa, 0);           /* RO */
-       if (dev_priv->chipset == 0xa0)
+       if (device->chipset == 0xa0)
                rep = 0xc;
        else
                rep = 4;
        for (i = 0; i < rep; i++) {
                /* SEEK */
-               if (IS_NVA3F(dev_priv->chipset))
+               if (IS_NVA3F(device->chipset))
                        xf_emit(ctx, 0x20, 0);  /* ffffffff */
                xf_emit(ctx, 0x200, 0); /* ffffffff */
                xf_emit(ctx, 4, 0);     /* 7f/ff, 0, 0, 0 */
@@ -2077,7 +2058,7 @@ nv50_graph_construct_gene_vfetch(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 0);             /* 0000000f VP_GP_BUILTIN_ATTR_EN */
        xf_emit(ctx, 1, 0);             /* ffffffff tesla UNK1A30 */
        /* SEEK */
-       if (IS_NVA3F(dev_priv->chipset))
+       if (IS_NVA3F(device->chipset))
                xf_emit(ctx, 7, 0);     /* weird... */
        else
                xf_emit(ctx, 5, 0);     /* weird... */
@@ -2086,13 +2067,13 @@ nv50_graph_construct_gene_vfetch(struct nouveau_grctx *ctx)
 static void
 nv50_graph_construct_gene_eng2d(struct nouveau_grctx *ctx)
 {
-       struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
+       struct nouveau_device *device = ctx->device;
        /* middle of strand 1 on pre-NVA0 [after vfetch], middle of strand 6 on NVAx */
        /* SEEK */
        xf_emit(ctx, 2, 0);             /* 0001ffff CLIP_X, CLIP_Y */
        xf_emit(ctx, 2, 0);             /* 0000ffff CLIP_W, CLIP_H */
        xf_emit(ctx, 1, 0);             /* 00000001 CLIP_ENABLE */
-       if (dev_priv->chipset < 0xa0) {
+       if (device->chipset < 0xa0) {
                /* this is useless on everything but the original NV50,
                 * guess they forgot to nuke it. Or just didn't bother. */
                xf_emit(ctx, 2, 0);     /* 0000ffff IFC_CLIP_X, Y */
@@ -2148,7 +2129,7 @@ nv50_graph_construct_gene_eng2d(struct nouveau_grctx *ctx)
 static void
 nv50_graph_construct_gene_csched(struct nouveau_grctx *ctx)
 {
-       struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
+       struct nouveau_device *device = ctx->device;
        /* middle of strand 1 on pre-NVA0 [after eng2d], middle of strand 0 on NVAx */
        /* SEEK */
        xf_emit(ctx, 2, 0);             /* 00007fff WINDOW_OFFSET_XY... what is it doing here??? */
@@ -2173,7 +2154,7 @@ nv50_graph_construct_gene_csched(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 2);             /* 00000003 REG_MODE */
        /* SEEK */
        xf_emit(ctx, 0x40, 0);          /* ffffffff USER_PARAM */
-       switch (dev_priv->chipset) {
+       switch (device->chipset) {
        case 0x50:
        case 0x92:
                xf_emit(ctx, 8, 0);     /* 7, 0, 0, 0, ... */
@@ -2247,7 +2228,7 @@ nv50_graph_construct_gene_csched(struct nouveau_grctx *ctx)
 static void
 nv50_graph_construct_gene_unk1cxx(struct nouveau_grctx *ctx)
 {
-       struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
+       struct nouveau_device *device = ctx->device;
        xf_emit(ctx, 2, 0);             /* 00007fff WINDOW_OFFSET_XY */
        xf_emit(ctx, 1, 0x3f800000);    /* ffffffff LINE_WIDTH */
        xf_emit(ctx, 1, 0);             /* 00000001 LINE_SMOOTH_ENABLE */
@@ -2277,9 +2258,9 @@ nv50_graph_construct_gene_unk1cxx(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 4);             /* 00000007 FP_CONTROL */
        xf_emit(ctx, 1, 0);             /* 00000001 ALPHA_TEST_ENABLE */
        xf_emit(ctx, 1, 0);             /* 00000007 ALPHA_TEST_FUNC */
-       if (IS_NVA3F(dev_priv->chipset))
+       if (IS_NVA3F(device->chipset))
                xf_emit(ctx, 1, 3);     /* 00000003 UNK16B4 */
-       else if (dev_priv->chipset >= 0xa0)
+       else if (device->chipset >= 0xa0)
                xf_emit(ctx, 1, 1);     /* 00000001 UNK16B4 */
        xf_emit(ctx, 1, 0);             /* 00000003 MULTISAMPLE_CTRL */
        xf_emit(ctx, 1, 0);             /* 00000003 tesla UNK0F90 */
@@ -2293,11 +2274,11 @@ nv50_graph_construct_gene_unk1cxx(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 0);             /* ffffffff POINT_SIZE */
        xf_emit(ctx, 1, 0);             /* 00000001 */
        xf_emit(ctx, 1, 0);             /* 00000007 tesla UNK0FB4 */
-       if (dev_priv->chipset != 0x50) {
+       if (device->chipset != 0x50) {
                xf_emit(ctx, 1, 0);     /* 3ff */
                xf_emit(ctx, 1, 1);     /* 00000001 tesla UNK1110 */
        }
-       if (IS_NVA3F(dev_priv->chipset))
+       if (IS_NVA3F(device->chipset))
                xf_emit(ctx, 1, 0);     /* 00000003 tesla UNK1928 */
        xf_emit(ctx, 0x10, 0);          /* ffffffff DEPTH_RANGE_NEAR */
        xf_emit(ctx, 0x10, 0x3f800000); /* ffffffff DEPTH_RANGE_FAR */
@@ -2316,11 +2297,11 @@ nv50_graph_construct_gene_unk1cxx(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 1);             /* 00000001 ZETA_ENABLE */
        xf_emit(ctx, 1, 0);             /* 00000001 VERTEX_TWO_SIDE_ENABLE */
        xf_emit(ctx, 4, 0xffff);        /* 0000ffff MSAA_MASK */
-       if (dev_priv->chipset != 0x50)
+       if (device->chipset != 0x50)
                xf_emit(ctx, 1, 3);     /* 00000003 tesla UNK1100 */
-       if (dev_priv->chipset < 0xa0)
+       if (device->chipset < 0xa0)
                xf_emit(ctx, 0x1c, 0);  /* RO */
-       else if (IS_NVA3F(dev_priv->chipset))
+       else if (IS_NVA3F(device->chipset))
                xf_emit(ctx, 0x9, 0);
        xf_emit(ctx, 1, 0);             /* 00000001 UNK1534 */
        xf_emit(ctx, 1, 0);             /* 00000001 LINE_SMOOTH_ENABLE */
@@ -2328,13 +2309,13 @@ nv50_graph_construct_gene_unk1cxx(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 0x00ffff00);    /* 00ffffff LINE_STIPPLE_PATTERN */
        xf_emit(ctx, 1, 0x1a);          /* 0000001f POLYGON_MODE */
        xf_emit(ctx, 1, 0);             /* 00000003 WINDOW_ORIGIN */
-       if (dev_priv->chipset != 0x50) {
+       if (device->chipset != 0x50) {
                xf_emit(ctx, 1, 3);     /* 00000003 tesla UNK1100 */
                xf_emit(ctx, 1, 0);     /* 3ff */
        }
        /* XXX: the following block could belong either to unk1cxx, or
         * to STRMOUT. Rather hard to tell. */
-       if (dev_priv->chipset < 0xa0)
+       if (device->chipset < 0xa0)
                xf_emit(ctx, 0x25, 0);
        else
                xf_emit(ctx, 0x3b, 0);
@@ -2343,18 +2324,18 @@ nv50_graph_construct_gene_unk1cxx(struct nouveau_grctx *ctx)
 static void
 nv50_graph_construct_gene_strmout(struct nouveau_grctx *ctx)
 {
-       struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
+       struct nouveau_device *device = ctx->device;
        xf_emit(ctx, 1, 0x102);         /* 0000ffff STRMOUT_BUFFER_CTRL */
        xf_emit(ctx, 1, 0);             /* ffffffff STRMOUT_PRIMITIVE_COUNT */
        xf_emit(ctx, 4, 4);             /* 000000ff STRMOUT_NUM_ATTRIBS */
-       if (dev_priv->chipset >= 0xa0) {
+       if (device->chipset >= 0xa0) {
                xf_emit(ctx, 4, 0);     /* ffffffff UNK1A8C */
                xf_emit(ctx, 4, 0);     /* ffffffff UNK1780 */
        }
        xf_emit(ctx, 1, 4);             /* 000000ff GP_RESULT_MAP_SIZE */
        xf_emit(ctx, 1, 4);             /* 0000007f VP_RESULT_MAP_SIZE */
        xf_emit(ctx, 1, 0);             /* 00000001 GP_ENABLE */
-       if (dev_priv->chipset == 0x50)
+       if (device->chipset == 0x50)
                xf_emit(ctx, 1, 0x3ff); /* 000003ff tesla UNK0D68 */
        else
                xf_emit(ctx, 1, 0x7ff); /* 000007ff tesla UNK0D68 */
@@ -2365,7 +2346,7 @@ nv50_graph_construct_gene_strmout(struct nouveau_grctx *ctx)
        xf_emit(ctx, 4, 0);             /* 000000ff STRMOUT_ADDRESS_HIGH */
        xf_emit(ctx, 4, 0);             /* ffffffff STRMOUT_ADDRESS_LOW */
        xf_emit(ctx, 4, 4);             /* 000000ff STRMOUT_NUM_ATTRIBS */
-       if (dev_priv->chipset >= 0xa0) {
+       if (device->chipset >= 0xa0) {
                xf_emit(ctx, 4, 0);     /* ffffffff UNK1A8C */
                xf_emit(ctx, 4, 0);     /* ffffffff UNK1780 */
        }
@@ -2385,12 +2366,12 @@ nv50_graph_construct_gene_strmout(struct nouveau_grctx *ctx)
 static void
 nv50_graph_construct_gene_ropm1(struct nouveau_grctx *ctx)
 {
-       struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
+       struct nouveau_device *device = ctx->device;
        xf_emit(ctx, 1, 0x4e3bfdf);     /* ffffffff UNK0D64 */
        xf_emit(ctx, 1, 0x4e3bfdf);     /* ffffffff UNK0DF4 */
        xf_emit(ctx, 1, 0);             /* 00000007 */
        xf_emit(ctx, 1, 0);             /* 000003ff */
-       if (IS_NVA3F(dev_priv->chipset))
+       if (IS_NVA3F(device->chipset))
                xf_emit(ctx, 1, 0x11);  /* 000000ff tesla UNK1968 */
        xf_emit(ctx, 1, 0);             /* ffffffff tesla UNK1A3C */
 }
@@ -2398,7 +2379,7 @@ nv50_graph_construct_gene_ropm1(struct nouveau_grctx *ctx)
 static void
 nv50_graph_construct_gene_ropm2(struct nouveau_grctx *ctx)
 {
-       struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
+       struct nouveau_device *device = ctx->device;
        /* SEEK */
        xf_emit(ctx, 1, 0);             /* 0000ffff DMA_QUERY */
        xf_emit(ctx, 1, 0x0fac6881);    /* 0fffffff RT_CONTROL */
@@ -2416,7 +2397,7 @@ nv50_graph_construct_gene_ropm2(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 0);             /* 00000001 eng2d UNK260 */
        xf_emit(ctx, 1, 0);             /* ff/3ff */
        xf_emit(ctx, 1, 0);             /* 00000007 */
-       if (IS_NVA3F(dev_priv->chipset))
+       if (IS_NVA3F(device->chipset))
                xf_emit(ctx, 1, 0x11);  /* 000000ff tesla UNK1968 */
        xf_emit(ctx, 1, 0);             /* ffffffff tesla UNK1A3C */
 }
@@ -2424,11 +2405,11 @@ nv50_graph_construct_gene_ropm2(struct nouveau_grctx *ctx)
 static void
 nv50_graph_construct_gene_ropc(struct nouveau_grctx *ctx)
 {
-       struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
+       struct nouveau_device *device = ctx->device;
        int magic2;
-       if (dev_priv->chipset == 0x50) {
+       if (device->chipset == 0x50) {
                magic2 = 0x00003e60;
-       } else if (!IS_NVA3F(dev_priv->chipset)) {
+       } else if (!IS_NVA3F(device->chipset)) {
                magic2 = 0x001ffe67;
        } else {
                magic2 = 0x00087e67;
@@ -2446,14 +2427,14 @@ nv50_graph_construct_gene_ropc(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 0);             /* 00000007 DEPTH_TEST_FUNC */
        xf_emit(ctx, 1, 0);             /* 00000001 DEPTH_TEST_ENABLE */
        xf_emit(ctx, 1, 0);             /* 00000001 DEPTH_WRITE_ENABLE */
-       if (IS_NVA3F(dev_priv->chipset))
+       if (IS_NVA3F(device->chipset))
                xf_emit(ctx, 1, 1);     /* 0000001f tesla UNK169C */
        xf_emit(ctx, 1, 0);             /* 00000007 STENCIL_FRONT_FUNC_FUNC */
        xf_emit(ctx, 1, 0);             /* 000000ff STENCIL_FRONT_FUNC_MASK */
        xf_emit(ctx, 1, 0);             /* 000000ff STENCIL_FRONT_MASK */
        xf_emit(ctx, 3, 0);             /* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */
        xf_emit(ctx, 1, 0);             /* 00000001 STENCIL_FRONT_ENABLE */
-       if (dev_priv->chipset >= 0xa0 && !IS_NVAAF(dev_priv->chipset))
+       if (device->chipset >= 0xa0 && !IS_NVAAF(device->chipset))
                xf_emit(ctx, 1, 0x15);  /* 000000ff */
        xf_emit(ctx, 1, 0);             /* 00000001 STENCIL_BACK_ENABLE */
        xf_emit(ctx, 1, 1);             /* 00000001 tesla UNK15B4 */
@@ -2462,14 +2443,14 @@ nv50_graph_construct_gene_ropc(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 0);             /* 0000000f ZETA_FORMAT */
        xf_emit(ctx, 1, 1);             /* 00000001 ZETA_ENABLE */
        xf_emit(ctx, 1, 0);             /* ffffffff tesla UNK1A3C */
-       if (dev_priv->chipset == 0x86 || dev_priv->chipset == 0x92 || dev_priv->chipset == 0x98 || dev_priv->chipset >= 0xa0) {
+       if (device->chipset == 0x86 || device->chipset == 0x92 || device->chipset == 0x98 || device->chipset >= 0xa0) {
                xf_emit(ctx, 3, 0);     /* ff, ffffffff, ffffffff */
                xf_emit(ctx, 1, 4);     /* 7 */
                xf_emit(ctx, 1, 0x400); /* fffffff */
                xf_emit(ctx, 1, 0x300); /* ffff */
                xf_emit(ctx, 1, 0x1001);        /* 1fff */
-               if (dev_priv->chipset != 0xa0) {
-                       if (IS_NVA3F(dev_priv->chipset))
+               if (device->chipset != 0xa0) {
+                       if (IS_NVA3F(device->chipset))
                                xf_emit(ctx, 1, 0);     /* 0000000f UNK15C8 */
                        else
                                xf_emit(ctx, 1, 0x15);  /* ff */
@@ -2547,7 +2528,7 @@ nv50_graph_construct_gene_ropc(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 1);             /* 00000001 ZETA_ENABLE */
        xf_emit(ctx, 1, 0);             /* ffffffff CLEAR_DEPTH */
        xf_emit(ctx, 1, 1);             /* 00000001 tesla UNK19CC */
-       if (dev_priv->chipset >= 0xa0) {
+       if (device->chipset >= 0xa0) {
                xf_emit(ctx, 2, 0);
                xf_emit(ctx, 1, 0x1001);
                xf_emit(ctx, 0xb, 0);
@@ -2564,7 +2545,7 @@ nv50_graph_construct_gene_ropc(struct nouveau_grctx *ctx)
        xf_emit(ctx, 7, 0);             /* 0000000f COLOR_MASK */
        xf_emit(ctx, 1, 0x11);          /* 3f/7f */
        xf_emit(ctx, 1, 0);             /* 00000001 LOGIC_OP_ENABLE */
-       if (dev_priv->chipset != 0x50) {
+       if (device->chipset != 0x50) {
                xf_emit(ctx, 1, 0);     /* 0000000f LOGIC_OP */
                xf_emit(ctx, 1, 0);     /* 000000ff */
        }
@@ -2581,7 +2562,7 @@ nv50_graph_construct_gene_ropc(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, magic2);        /* 001fffff tesla UNK0F78 */
        xf_emit(ctx, 1, 0);             /* ffffffff tesla UNK1A3C */
        xf_emit(ctx, 1, 0x0fac6881);    /* 0fffffff RT_CONTROL */
-       if (IS_NVA3F(dev_priv->chipset)) {
+       if (IS_NVA3F(device->chipset)) {
                xf_emit(ctx, 1, 0);     /* 00000001 tesla UNK12E4 */
                xf_emit(ctx, 8, 1);     /* 00000007 IBLEND_EQUATION_RGB */
                xf_emit(ctx, 8, 1);     /* 00000007 IBLEND_EQUATION_ALPHA */
@@ -2600,7 +2581,7 @@ nv50_graph_construct_gene_ropc(struct nouveau_grctx *ctx)
                xf_emit(ctx, 1, 1);     /* 0000001f tesla UNK169C */
                xf_emit(ctx, 1, 0);     /* 00000001 */
                xf_emit(ctx, 1, 0);     /* 000003ff */
-       } else if (dev_priv->chipset >= 0xa0) {
+       } else if (device->chipset >= 0xa0) {
                xf_emit(ctx, 2, 0);     /* 00000001 */
                xf_emit(ctx, 1, 0);     /* 00000007 */
                xf_emit(ctx, 1, 0);     /* 00000003 */
@@ -2614,7 +2595,7 @@ nv50_graph_construct_gene_ropc(struct nouveau_grctx *ctx)
        xf_emit(ctx, 4, 0);             /* ffffffff CLEAR_COLOR */
        xf_emit(ctx, 4, 0);             /* ffffffff BLEND_COLOR A R G B */
        xf_emit(ctx, 1, 0);             /* 00000fff eng2d UNK2B0 */
-       if (dev_priv->chipset >= 0xa0)
+       if (device->chipset >= 0xa0)
                xf_emit(ctx, 2, 0);     /* 00000001 */
        xf_emit(ctx, 1, 0);             /* 000003ff */
        xf_emit(ctx, 8, 0);             /* 00000001 BLEND_ENABLE */
@@ -2628,9 +2609,9 @@ nv50_graph_construct_gene_ropc(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 0);             /* 00000001 UNK19C0 */
        xf_emit(ctx, 1, 0);             /* 00000001 LOGIC_OP_ENABLE */
        xf_emit(ctx, 1, 0);             /* 0000000f LOGIC_OP */
-       if (dev_priv->chipset >= 0xa0)
+       if (device->chipset >= 0xa0)
                xf_emit(ctx, 1, 0);     /* 00000001 UNK12E4? NVA3+ only? */
-       if (IS_NVA3F(dev_priv->chipset)) {
+       if (IS_NVA3F(device->chipset)) {
                xf_emit(ctx, 8, 1);     /* 00000001 IBLEND_UNK00 */
                xf_emit(ctx, 8, 1);     /* 00000007 IBLEND_EQUATION_RGB */
                xf_emit(ctx, 8, 2);     /* 0000001f IBLEND_FUNC_SRC_RGB */
@@ -2659,9 +2640,9 @@ nv50_graph_construct_gene_ropc(struct nouveau_grctx *ctx)
 static void
 nv50_graph_construct_xfer_unk84xx(struct nouveau_grctx *ctx)
 {
-       struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
+       struct nouveau_device *device = ctx->device;
        int magic3;
-       switch (dev_priv->chipset) {
+       switch (device->chipset) {
        case 0x50:
                magic3 = 0x1000;
                break;
@@ -2681,16 +2662,16 @@ nv50_graph_construct_xfer_unk84xx(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 0);             /* 00000001 GP_ENABLE */
        xf_emit(ctx, 1, 0);             /* ffffffff tesla UNK1A30 */
        xf_emit(ctx, 1, 0);             /* 111/113[NVA0+] */
-       if (IS_NVA3F(dev_priv->chipset))
+       if (IS_NVA3F(device->chipset))
                xf_emit(ctx, 0x1f, 0);  /* ffffffff */
-       else if (dev_priv->chipset >= 0xa0)
+       else if (device->chipset >= 0xa0)
                xf_emit(ctx, 0x0f, 0);  /* ffffffff */
        else
                xf_emit(ctx, 0x10, 0);  /* fffffff VP_RESULT_MAP_1 up */
        xf_emit(ctx, 2, 0);             /* f/1f[NVA3], fffffff/ffffffff[NVA0+] */
        xf_emit(ctx, 1, 4);             /* 7f/ff VP_REG_ALLOC_RESULT */
        xf_emit(ctx, 1, 4);             /* 7f/ff VP_RESULT_MAP_SIZE */
-       if (dev_priv->chipset >= 0xa0)
+       if (device->chipset >= 0xa0)
                xf_emit(ctx, 1, 0x03020100);    /* ffffffff */
        else
                xf_emit(ctx, 1, 0x00608080);    /* fffffff VP_RESULT_MAP_0 */
@@ -2733,11 +2714,11 @@ nv50_graph_construct_xfer_unk84xx(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 0);             /* 00000001 GP_ENABLE */
        xf_emit(ctx, 1, 0);             /* ffffffff tesla UNK1A30 */
        xf_emit(ctx, 1, 0);             /* 111/113 */
-       if (dev_priv->chipset == 0x94 || dev_priv->chipset == 0x96)
+       if (device->chipset == 0x94 || device->chipset == 0x96)
                xf_emit(ctx, 0x1020, 0);        /* 4 x (0x400 x 0xffffffff, ff, 0, 0, 0, 4 x ffffffff) */
-       else if (dev_priv->chipset < 0xa0)
+       else if (device->chipset < 0xa0)
                xf_emit(ctx, 0xa20, 0); /* 4 x (0x280 x 0xffffffff, ff, 0, 0, 0, 4 x ffffffff) */
-       else if (!IS_NVA3F(dev_priv->chipset))
+       else if (!IS_NVA3F(device->chipset))
                xf_emit(ctx, 0x210, 0); /* ffffffff */
        else
                xf_emit(ctx, 0x410, 0); /* ffffffff */
@@ -2751,12 +2732,12 @@ nv50_graph_construct_xfer_unk84xx(struct nouveau_grctx *ctx)
 static void
 nv50_graph_construct_xfer_tprop(struct nouveau_grctx *ctx)
 {
-       struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
+       struct nouveau_device *device = ctx->device;
        int magic1, magic2;
-       if (dev_priv->chipset == 0x50) {
+       if (device->chipset == 0x50) {
                magic1 = 0x3ff;
                magic2 = 0x00003e60;
-       } else if (!IS_NVA3F(dev_priv->chipset)) {
+       } else if (!IS_NVA3F(device->chipset)) {
                magic1 = 0x7ff;
                magic2 = 0x001ffe67;
        } else {
@@ -2766,7 +2747,7 @@ nv50_graph_construct_xfer_tprop(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 0);             /* 00000007 ALPHA_TEST_FUNC */
        xf_emit(ctx, 1, 0);             /* ffffffff ALPHA_TEST_REF */
        xf_emit(ctx, 1, 0);             /* 00000001 ALPHA_TEST_ENABLE */
-       if (IS_NVA3F(dev_priv->chipset))
+       if (IS_NVA3F(device->chipset))
                xf_emit(ctx, 1, 1);     /* 0000000f UNK16A0 */
        xf_emit(ctx, 1, 0);             /* 7/f MULTISAMPLE_SAMPLES_LOG2 */
        xf_emit(ctx, 1, 0);             /* 00000001 tesla UNK1534 */
@@ -2800,11 +2781,11 @@ nv50_graph_construct_xfer_tprop(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 1);             /* 00000001 SIFC_BITMAP_WRITE_BIT0_ENABLE */
        xf_emit(ctx, 1, 0);             /* 00000007 ALPHA_TEST_FUNC */
        xf_emit(ctx, 1, 0);             /* 00000001 ALPHA_TEST_ENABLE */
-       if (IS_NVA3F(dev_priv->chipset)) {
+       if (IS_NVA3F(device->chipset)) {
                xf_emit(ctx, 1, 3);     /* 00000003 tesla UNK16B4 */
                xf_emit(ctx, 1, 0);     /* 00000003 */
                xf_emit(ctx, 1, 0);     /* 00000003 tesla UNK1298 */
-       } else if (dev_priv->chipset >= 0xa0) {
+       } else if (device->chipset >= 0xa0) {
                xf_emit(ctx, 1, 1);     /* 00000001 tesla UNK16B4 */
                xf_emit(ctx, 1, 0);     /* 00000003 */
        } else {
@@ -2818,7 +2799,7 @@ nv50_graph_construct_xfer_tprop(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 1);             /* 0000001f BLEND_FUNC_DST_RGB */
        xf_emit(ctx, 1, 1);             /* 00000007 BLEND_EQUATION_RGB */
        xf_emit(ctx, 1, 2);             /* 0000001f BLEND_FUNC_SRC_RGB */
-       if (IS_NVA3F(dev_priv->chipset)) {
+       if (IS_NVA3F(device->chipset)) {
                xf_emit(ctx, 1, 0);     /* 00000001 UNK12E4 */
                xf_emit(ctx, 8, 1);     /* 00000007 IBLEND_EQUATION_RGB */
                xf_emit(ctx, 8, 1);     /* 00000007 IBLEND_EQUATION_ALPHA */
@@ -2846,7 +2827,7 @@ nv50_graph_construct_xfer_tprop(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 0xcf);          /* 000000ff SIFC_FORMAT */
        xf_emit(ctx, 1, 0xcf);          /* 000000ff DRAW_COLOR_FORMAT */
        xf_emit(ctx, 1, 0xcf);          /* 000000ff SRC_FORMAT */
-       if (IS_NVA3F(dev_priv->chipset))
+       if (IS_NVA3F(device->chipset))
                xf_emit(ctx, 1, 1);     /* 0000001f tesla UNK169C */
        xf_emit(ctx, 1, 0);             /* ffffffff tesla UNK1A3C */
        xf_emit(ctx, 1, 0);             /* 7/f[NVA3] MULTISAMPLE_SAMPLES_LOG2 */
@@ -2870,9 +2851,9 @@ nv50_graph_construct_xfer_tprop(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 0);             /* 00000001 DEPTH_TEST_ENABLE */
        xf_emit(ctx, 1, 0x11);          /* 3f/7f DST_FORMAT */
        xf_emit(ctx, 1, 1);             /* 00000001 DST_LINEAR */
-       if (IS_NVA3F(dev_priv->chipset))
+       if (IS_NVA3F(device->chipset))
                xf_emit(ctx, 1, 1);     /* 0000001f tesla UNK169C */
-       if (dev_priv->chipset == 0x50)
+       if (device->chipset == 0x50)
                xf_emit(ctx, 1, 0);     /* ff */
        else
                xf_emit(ctx, 3, 0);     /* 1, 7, 3ff */
@@ -2907,7 +2888,7 @@ nv50_graph_construct_xfer_tprop(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 1);             /* 00000001 ZETA_ENABLE */
        xf_emit(ctx, 1, 0);             /* 00000007 */
        xf_emit(ctx, 1, 0);             /* ffffffff tesla UNK1A3C */
-       if (IS_NVA3F(dev_priv->chipset))
+       if (IS_NVA3F(device->chipset))
                xf_emit(ctx, 1, 1);     /* 0000001f tesla UNK169C */
        xf_emit(ctx, 8, 0);             /* 0000ffff DMA_COLOR */
        xf_emit(ctx, 1, 0);             /* 0000ffff DMA_GLOBAL */
@@ -2945,7 +2926,7 @@ nv50_graph_construct_xfer_tprop(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 0);             /* 0001ffff GP_BUILTIN_RESULT_EN */
        xf_emit(ctx, 1, 0);             /* 00000003 UNK0F90 */
        xf_emit(ctx, 1, 0);             /* 00000007 */
-       if (IS_NVA3F(dev_priv->chipset))
+       if (IS_NVA3F(device->chipset))
                xf_emit(ctx, 1, 1);     /* 0000001f tesla UNK169C */
        xf_emit(ctx, 1, magic2);        /* 001fffff tesla UNK0F78 */
        xf_emit(ctx, 1, 0);             /* 7/f MULTISAMPLE_SAMPLES_LOG2 */
@@ -2974,7 +2955,7 @@ nv50_graph_construct_xfer_tprop(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 0x1001);        /* 00001fff ZETA_ARRAY_MODE */
        xf_emit(ctx, 1, 0);             /* ffffffff tesla UNK1A3C */
        xf_emit(ctx, 1, 0);             /* 7/f MULTISAMPLE_SAMPLES_LOG2 */
-       if (IS_NVA3F(dev_priv->chipset))
+       if (IS_NVA3F(device->chipset))
                xf_emit(ctx, 1, 0);     /* 00000001 */
        xf_emit(ctx, 1, 0);             /* ffff0ff3 */
        xf_emit(ctx, 1, 0x11);          /* 3f/7f RT_FORMAT */
@@ -2988,14 +2969,14 @@ nv50_graph_construct_xfer_tprop(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 0);             /* 00000001 FRAMEBUFFER_SRGB */
        xf_emit(ctx, 1, 0);             /* 7 */
        xf_emit(ctx, 1, 0);             /* 00000001 LOGIC_OP_ENABLE */
-       if (IS_NVA3F(dev_priv->chipset)) {
+       if (IS_NVA3F(device->chipset)) {
                xf_emit(ctx, 1, 0);     /* 00000001 UNK1140 */
                xf_emit(ctx, 1, 1);     /* 0000001f tesla UNK169C */
        }
        xf_emit(ctx, 1, 0);             /* 7/f MULTISAMPLE_SAMPLES_LOG2 */
        xf_emit(ctx, 1, 0);             /* 00000001 UNK1534 */
        xf_emit(ctx, 1, 0);             /* ffff0ff3 */
-       if (dev_priv->chipset >= 0xa0)
+       if (device->chipset >= 0xa0)
                xf_emit(ctx, 1, 0x0fac6881);    /* fffffff */
        xf_emit(ctx, 1, magic2);        /* 001fffff tesla UNK0F78 */
        xf_emit(ctx, 1, 0);             /* 00000001 DEPTH_BOUNDS_EN */
@@ -3012,12 +2993,12 @@ nv50_graph_construct_xfer_tprop(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 0);             /* 00000001 SAMPLECNT_ENABLE */
        xf_emit(ctx, 1, 0);             /* 0000000f ZETA_FORMAT */
        xf_emit(ctx, 1, 1);             /* 00000001 ZETA_ENABLE */
-       if (IS_NVA3F(dev_priv->chipset)) {
+       if (IS_NVA3F(device->chipset)) {
                xf_emit(ctx, 1, 1);     /* 0000001f tesla UNK169C */
                xf_emit(ctx, 1, 0);     /* 0000000f tesla UNK15C8 */
        }
        xf_emit(ctx, 1, 0);             /* ffffffff tesla UNK1A3C */
-       if (dev_priv->chipset >= 0xa0) {
+       if (device->chipset >= 0xa0) {
                xf_emit(ctx, 3, 0);             /* 7/f, 1, ffff0ff3 */
                xf_emit(ctx, 1, 0xfac6881);     /* fffffff */
                xf_emit(ctx, 4, 0);             /* 1, 1, 1, 3ff */
@@ -3027,7 +3008,7 @@ nv50_graph_construct_xfer_tprop(struct nouveau_grctx *ctx)
                xf_emit(ctx, 2, 0);             /* 7, f */
                xf_emit(ctx, 1, 1);             /* 1 */
                xf_emit(ctx, 1, 0);             /* 7/f */
-               if (IS_NVA3F(dev_priv->chipset))
+               if (IS_NVA3F(device->chipset))
                        xf_emit(ctx, 0x9, 0);   /* 1 */
                else
                        xf_emit(ctx, 0x8, 0);   /* 1 */
@@ -3041,7 +3022,7 @@ nv50_graph_construct_xfer_tprop(struct nouveau_grctx *ctx)
                xf_emit(ctx, 1, 0x11);          /* 7f */
                xf_emit(ctx, 1, 1);             /* 1 */
                xf_emit(ctx, 5, 0);             /* 1, 7, 3ff, 3, 7 */
-               if (IS_NVA3F(dev_priv->chipset)) {
+               if (IS_NVA3F(device->chipset)) {
                        xf_emit(ctx, 1, 0);     /* 00000001 UNK1140 */
                        xf_emit(ctx, 1, 1);     /* 0000001f tesla UNK169C */
                }
@@ -3051,15 +3032,15 @@ nv50_graph_construct_xfer_tprop(struct nouveau_grctx *ctx)
 static void
 nv50_graph_construct_xfer_tex(struct nouveau_grctx *ctx)
 {
-       struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
+       struct nouveau_device *device = ctx->device;
        xf_emit(ctx, 2, 0);             /* 1 LINKED_TSC. yes, 2. */
-       if (dev_priv->chipset != 0x50)
+       if (device->chipset != 0x50)
                xf_emit(ctx, 1, 0);     /* 3 */
        xf_emit(ctx, 1, 1);             /* 1ffff BLIT_DU_DX_INT */
        xf_emit(ctx, 1, 0);             /* fffff BLIT_DU_DX_FRACT */
        xf_emit(ctx, 1, 1);             /* 1ffff BLIT_DV_DY_INT */
        xf_emit(ctx, 1, 0);             /* fffff BLIT_DV_DY_FRACT */
-       if (dev_priv->chipset == 0x50)
+       if (device->chipset == 0x50)
                xf_emit(ctx, 1, 0);     /* 3 BLIT_CONTROL */
        else
                xf_emit(ctx, 2, 0);     /* 3ff, 1 */
@@ -3071,13 +3052,13 @@ nv50_graph_construct_xfer_tex(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 0x10100);       /* ffffffff SRC_TIC_5 */
        xf_emit(ctx, 1, 0x02800000);    /* ffffffff SRC_TIC_6 */
        xf_emit(ctx, 1, 0);             /* ffffffff SRC_TIC_7 */
-       if (dev_priv->chipset == 0x50) {
+       if (device->chipset == 0x50) {
                xf_emit(ctx, 1, 0);     /* 00000001 turing UNK358 */
                xf_emit(ctx, 1, 0);     /* ffffffff tesla UNK1A34? */
                xf_emit(ctx, 1, 0);     /* 00000003 turing UNK37C tesla UNK1690 */
                xf_emit(ctx, 1, 0);     /* 00000003 BLIT_CONTROL */
                xf_emit(ctx, 1, 0);     /* 00000001 turing UNK32C tesla UNK0F94 */
-       } else if (!IS_NVAAF(dev_priv->chipset)) {
+       } else if (!IS_NVAAF(device->chipset)) {
                xf_emit(ctx, 1, 0);     /* ffffffff tesla UNK1A34? */
                xf_emit(ctx, 1, 0);     /* 00000003 */
                xf_emit(ctx, 1, 0);     /* 000003ff */
@@ -3097,7 +3078,7 @@ nv50_graph_construct_xfer_tex(struct nouveau_grctx *ctx)
 static void
 nv50_graph_construct_xfer_unk8cxx(struct nouveau_grctx *ctx)
 {
-       struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
+       struct nouveau_device *device = ctx->device;
        xf_emit(ctx, 1, 0);             /* 00000001 UNK1534 */
        xf_emit(ctx, 1, 0);             /* 7/f MULTISAMPLE_SAMPLES_LOG2 */
        xf_emit(ctx, 2, 0);             /* 7, ffff0ff3 */
@@ -3109,7 +3090,7 @@ nv50_graph_construct_xfer_unk8cxx(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 0);             /* 00000001 LINE_STIPPLE_ENABLE */
        xf_emit(ctx, 1, 0x00ffff00);    /* 00ffffff LINE_STIPPLE_PATTERN */
        xf_emit(ctx, 1, 1);             /* 00000001 tesla UNK0F98 */
-       if (IS_NVA3F(dev_priv->chipset))
+       if (IS_NVA3F(device->chipset))
                xf_emit(ctx, 1, 1);     /* 0000001f tesla UNK169C */
        xf_emit(ctx, 1, 0);             /* 00000003 tesla UNK1668 */
        xf_emit(ctx, 1, 0);             /* 00000001 LINE_STIPPLE_ENABLE */
@@ -3136,8 +3117,8 @@ nv50_graph_construct_xfer_unk8cxx(struct nouveau_grctx *ctx)
 static void
 nv50_graph_construct_xfer_tp(struct nouveau_grctx *ctx)
 {
-       struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
-       if (dev_priv->chipset < 0xa0) {
+       struct nouveau_device *device = ctx->device;
+       if (device->chipset < 0xa0) {
                nv50_graph_construct_xfer_unk84xx(ctx);
                nv50_graph_construct_xfer_tprop(ctx);
                nv50_graph_construct_xfer_tex(ctx);
@@ -3153,9 +3134,9 @@ nv50_graph_construct_xfer_tp(struct nouveau_grctx *ctx)
 static void
 nv50_graph_construct_xfer_mpc(struct nouveau_grctx *ctx)
 {
-       struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
+       struct nouveau_device *device = ctx->device;
        int i, mpcnt = 2;
-       switch (dev_priv->chipset) {
+       switch (device->chipset) {
                case 0x98:
                case 0xaa:
                        mpcnt = 1;
@@ -3182,34 +3163,34 @@ nv50_graph_construct_xfer_mpc(struct nouveau_grctx *ctx)
                xf_emit(ctx, 1, 0x80);          /* ffffffff tesla UNK1404 */
                xf_emit(ctx, 1, 0x80007004);    /* ffffffff tesla UNK12B0 */
                xf_emit(ctx, 1, 0x04000400);    /* ffffffff */
-               if (dev_priv->chipset >= 0xa0)
+               if (device->chipset >= 0xa0)
                        xf_emit(ctx, 1, 0xc0);  /* 00007fff tesla UNK152C */
                xf_emit(ctx, 1, 0x1000);        /* 0000ffff tesla UNK0D60 */
                xf_emit(ctx, 1, 0);             /* ff/3ff */
                xf_emit(ctx, 1, 0);             /* ffffffff tesla UNK1A30 */
-               if (dev_priv->chipset == 0x86 || dev_priv->chipset == 0x98 || dev_priv->chipset == 0xa8 || IS_NVAAF(dev_priv->chipset)) {
+               if (device->chipset == 0x86 || device->chipset == 0x98 || device->chipset == 0xa8 || IS_NVAAF(device->chipset)) {
                        xf_emit(ctx, 1, 0xe00);         /* 7fff */
                        xf_emit(ctx, 1, 0x1e00);        /* 7fff */
                }
                xf_emit(ctx, 1, 1);             /* 000000ff VP_REG_ALLOC_TEMP */
                xf_emit(ctx, 1, 0);             /* 00000001 LINKED_TSC */
                xf_emit(ctx, 1, 0);             /* 00000001 GP_ENABLE */
-               if (dev_priv->chipset == 0x50)
+               if (device->chipset == 0x50)
                        xf_emit(ctx, 2, 0x1000);        /* 7fff tesla UNK141C */
                xf_emit(ctx, 1, 1);             /* 000000ff GP_REG_ALLOC_TEMP */
                xf_emit(ctx, 1, 0);             /* 00000001 GP_ENABLE */
                xf_emit(ctx, 1, 4);             /* 000000ff FP_REG_ALLOC_TEMP */
                xf_emit(ctx, 1, 2);             /* 00000003 REG_MODE */
-               if (IS_NVAAF(dev_priv->chipset))
+               if (IS_NVAAF(device->chipset))
                        xf_emit(ctx, 0xb, 0);   /* RO */
-               else if (dev_priv->chipset >= 0xa0)
+               else if (device->chipset >= 0xa0)
                        xf_emit(ctx, 0xc, 0);   /* RO */
                else
                        xf_emit(ctx, 0xa, 0);   /* RO */
        }
        xf_emit(ctx, 1, 0x08100c12);            /* 1fffffff FP_INTERPOLANT_CTRL */
        xf_emit(ctx, 1, 0);                     /* ff/3ff */
-       if (dev_priv->chipset >= 0xa0) {
+       if (device->chipset >= 0xa0) {
                xf_emit(ctx, 1, 0x1fe21);       /* 0003ffff tesla UNK0FAC */
        }
        xf_emit(ctx, 3, 0);                     /* 7fff, 0, 0 */
@@ -3223,7 +3204,7 @@ nv50_graph_construct_xfer_mpc(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 0);                     /* ffffffff SHARED_SIZE */
        xf_emit(ctx, 1, 0x1fe21);               /* 1ffff/3ffff[NVA0+] tesla UNk0FAC */
        xf_emit(ctx, 1, 0);                     /* ffffffff tesla UNK1A34 */
-       if (IS_NVA3F(dev_priv->chipset))
+       if (IS_NVA3F(device->chipset))
                xf_emit(ctx, 1, 1);             /* 0000001f tesla UNK169C */
        xf_emit(ctx, 1, 0);                     /* ff/3ff */
        xf_emit(ctx, 1, 0);                     /* 1 LINKED_TSC */
@@ -3238,7 +3219,7 @@ nv50_graph_construct_xfer_mpc(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 0);                     /* 00000007 */
        xf_emit(ctx, 1, 0xfac6881);             /* 0fffffff RT_CONTROL */
        xf_emit(ctx, 1, 0);                     /* 00000003 MULTISAMPLE_CTRL */
-       if (IS_NVA3F(dev_priv->chipset))
+       if (IS_NVA3F(device->chipset))
                xf_emit(ctx, 1, 3);             /* 00000003 tesla UNK16B4 */
        xf_emit(ctx, 1, 0);                     /* 00000001 ALPHA_TEST_ENABLE */
        xf_emit(ctx, 1, 0);                     /* 00000007 ALPHA_TEST_FUNC */
@@ -3253,7 +3234,7 @@ nv50_graph_construct_xfer_mpc(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 1);                     /* 0000001f BLEND_FUNC_DST_ALPHA */
        xf_emit(ctx, 1, 1);                     /* 00000007 BLEND_EQUATION_ALPHA */
        xf_emit(ctx, 1, 1);                     /* 00000001 UNK133C */
-       if (IS_NVA3F(dev_priv->chipset)) {
+       if (IS_NVA3F(device->chipset)) {
                xf_emit(ctx, 1, 0);             /* 00000001 UNK12E4 */
                xf_emit(ctx, 8, 2);             /* 0000001f IBLEND_FUNC_SRC_RGB */
                xf_emit(ctx, 8, 1);             /* 0000001f IBLEND_FUNC_DST_RGB */
@@ -3268,11 +3249,11 @@ nv50_graph_construct_xfer_mpc(struct nouveau_grctx *ctx)
        xf_emit(ctx, 1, 0);                     /* 00000003 tesla UNK0F90 */
        xf_emit(ctx, 1, 4);                     /* 000000ff FP_RESULT_COUNT */
        /* XXX: demagic this part some day */
-       if (dev_priv->chipset == 0x50)
+       if (device->chipset == 0x50)
                xf_emit(ctx, 0x3a0, 0);
-       else if (dev_priv->chipset < 0x94)
+       else if (device->chipset < 0x94)
                xf_emit(ctx, 0x3a2, 0);
-       else if (dev_priv->chipset == 0x98 || dev_priv->chipset == 0xaa)
+       else if (device->chipset == 0x98 || device->chipset == 0xaa)
                xf_emit(ctx, 0x39f, 0);
        else
                xf_emit(ctx, 0x3a3, 0);
@@ -3285,15 +3266,15 @@ nv50_graph_construct_xfer_mpc(struct nouveau_grctx *ctx)
 static void
 nv50_graph_construct_xfer2(struct nouveau_grctx *ctx)
 {
-       struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
+       struct nouveau_device *device = ctx->device;
        int i;
-       uint32_t offset;
-       uint32_t units = nv_rd32 (ctx->dev, 0x1540);
+       u32 offset;
+       u32 units = nv_rd32 (ctx->device, 0x1540);
        int size = 0;
 
        offset = (ctx->ctxvals_pos+0x3f)&~0x3f;
 
-       if (dev_priv->chipset < 0xa0) {
+       if (device->chipset < 0xa0) {
                for (i = 0; i < 8; i++) {
                        ctx->ctxvals_pos = offset + i;
                        /* that little bugger belongs to csched. No idea