drm/nouveau: port all engines to new engine module format

[deliverable/linux.git] / drivers / gpu / drm / nouveau / nv50_fence.c

diff --git a/drivers/gpu/drm/nouveau/nv50_fence.c b/drivers/gpu/drm/nouveau/nv50_fence.c
index 10aa04f26b830ef24c6cf39fac7be2c9dcc0faf8..e717aaaf62c67fff53a41e4feb0919167bf9a6dc 100644 (file)
--- a/drivers/gpu/drm/nouveau/nv50_fence.c
+++ b/drivers/gpu/drm/nouveau/nv50_fence.c
@@ -22,12 +22,12 @@
  * Authors: Ben Skeggs <bskeggs@redhat.com>
  */
 
-#include "drmP.h"
-#include "nouveau_drv.h"
+#include <core/object.h>
+#include <core/class.h>
+
+#include "nouveau_drm.h"
 #include "nouveau_dma.h"
-#include <core/ramht.h>
 #include "nouveau_fence.h"
-#include "nv50_display.h"
 
 struct nv50_fence_chan {
        struct nouveau_fence_chan base;
@@ -43,12 +43,11 @@ struct nv50_fence_priv {
 static int
 nv50_fence_context_new(struct nouveau_channel *chan)
 {
-       struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
-       struct nv50_fence_priv *priv = dev_priv->fence.func;
+       struct nv50_fence_priv *priv = chan->drm->fence;
        struct nv50_fence_chan *fctx;
        struct ttm_mem_reg *mem = &priv->bo->bo.mem;
-       struct nouveau_gpuobj *obj;
-       int ret = 0, i;
+       struct nouveau_object *object;
+       int ret, i;
 
        fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
        if (!fctx)
@@ -56,30 +55,29 @@ nv50_fence_context_new(struct nouveau_channel *chan)
 
        nouveau_fence_context_new(&fctx->base);
 
-       ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_FROM_MEMORY,
-                                    mem->start * PAGE_SIZE, mem->size,
-                                    NV_MEM_ACCESS_RW,
-                                    NV_MEM_TARGET_VRAM, &obj);
-       if (!ret) {
-               ret = nouveau_ramht_insert(chan, NvSema, obj);
-               nouveau_gpuobj_ref(NULL, &obj);
-       }
+       ret = nouveau_object_new(nv_object(chan->cli), chan->handle,
+                                NvSema, 0x0002,
+                                &(struct nv_dma_class) {
+                                       .flags = NV_DMA_TARGET_VRAM |
+                                                NV_DMA_ACCESS_RDWR,
+                                       .start = mem->start * PAGE_SIZE,
+                                       .limit = mem->size - 1,
+                                }, sizeof(struct nv_dma_class),
+                                &object);
 
        /* dma objects for display sync channel semaphore blocks */
-       for (i = 0; i < chan->dev->mode_config.num_crtc; i++) {
-               struct nv50_display *pdisp = nv50_display(chan->dev);
-               struct nv50_display_crtc *dispc = &pdisp->crtc[i];
-               struct nouveau_gpuobj *obj = NULL;
-
-               ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
-                                            dispc->sem.bo->bo.offset, 0x1000,
-                                            NV_MEM_ACCESS_RW,
-                                            NV_MEM_TARGET_VRAM, &obj);
-               if (ret)
-                       break;
-
-               ret = nouveau_ramht_insert(chan, NvEvoSema0 + i, obj);
-               nouveau_gpuobj_ref(NULL, &obj);
+       for (i = 0; !ret && i < chan->drm->dev->mode_config.num_crtc; i++) {
+               struct nouveau_bo *bo = nv50sema(chan->drm->dev, i);
+
+               ret = nouveau_object_new(nv_object(chan->cli), chan->handle,
+                                        NvEvoSema0 + i, 0x003d,
+                                        &(struct nv_dma_class) {
+                                               .flags = NV_DMA_TARGET_VRAM |
+                                                        NV_DMA_ACCESS_RDWR,
+                                               .start = bo->bo.offset,
+                                               .limit = bo->bo.offset + 0xfff,
+                                        }, sizeof(struct nv_dma_class),
+                                        &object);
        }
 
        if (ret)
@@ -88,13 +86,12 @@ nv50_fence_context_new(struct nouveau_channel *chan)
 }
 
 int
-nv50_fence_create(struct drm_device *dev)
+nv50_fence_create(struct nouveau_drm *drm)
 {
-       struct drm_nouveau_private *dev_priv = dev->dev_private;
        struct nv50_fence_priv *priv;
        int ret = 0;
 
-       priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+       priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
        if (!priv)
                return -ENOMEM;
 
@@ -104,10 +101,9 @@ nv50_fence_create(struct drm_device *dev)
        priv->base.emit = nv10_fence_emit;
        priv->base.read = nv10_fence_read;
        priv->base.sync = nv17_fence_sync;
-       dev_priv->fence.func = &priv->base;
        spin_lock_init(&priv->lock);
 
-       ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
+       ret = nouveau_bo_new(drm->dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
                             0, 0x0000, NULL, &priv->bo);
        if (!ret) {
                ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM);
@@ -117,9 +113,12 @@ nv50_fence_create(struct drm_device *dev)
                        nouveau_bo_ref(NULL, &priv->bo);
        }
 
-       if (ret == 0)
+       if (ret == 0) {
                nouveau_bo_wr32(priv->bo, 0x000, 0x00000000);
-       else
-               nv10_fence_destroy(dev);
+               priv->base.sync = nv17_fence_sync;
+       }
+
+       if (ret)
+               nv10_fence_destroy(drm);
        return ret;
 }