drm/nouveau/pm: implement DDR2/DDR3/GDDR3/GDDR5 MR generation and validation

[deliverable/linux.git] / drivers / gpu / drm / nouveau / nv50_vram.c

diff --git a/drivers/gpu/drm/nouveau/nv50_vram.c b/drivers/gpu/drm/nouveau/nv50_vram.c
index 84069669461187d88f6787149125080fd57a8a69..a52b9a51e01095fea8020c1ac9cd196d8b2031f5 100644 (file)
--- a/drivers/gpu/drm/nouveau/nv50_vram.c
+++ b/drivers/gpu/drm/nouveau/nv50_vram.c
@@ -195,10 +195,10 @@ nv50_vram_init(struct drm_device *dev)
        switch (pfb714 & 0x00000007) {
        case 0: dev_priv->vram_type = NV_MEM_TYPE_DDR1; break;
        case 1:
-               if (0 /* some currently unknown condition */)
-                       dev_priv->vram_type = NV_MEM_TYPE_DDR2;
-               else
+               if (nouveau_mem_vbios_type(dev) == NV_MEM_TYPE_DDR3)
                        dev_priv->vram_type = NV_MEM_TYPE_DDR3;
+               else
+                       dev_priv->vram_type = NV_MEM_TYPE_DDR2;
                break;
        case 2: dev_priv->vram_type = NV_MEM_TYPE_GDDR3; break;
        case 3: dev_priv->vram_type = NV_MEM_TYPE_GDDR4; break;
@@ -207,6 +207,7 @@ nv50_vram_init(struct drm_device *dev)
                break;
        }
 
+       dev_priv->vram_rank_B = (nv_rd32(dev, NV04_PFB_CFG0) & 0x100) >> 8;
        dev_priv->vram_size  = nv_rd32(dev, 0x10020c);
        dev_priv->vram_size |= (dev_priv->vram_size & 0xff) << 32;
        dev_priv->vram_size &= 0xffffffff00ULL;