drm/ttm: Hide the implementation details of reservation

[deliverable/linux.git] / drivers / gpu / drm / radeon / cik.c

diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index e22be8458d92783f426a699d2e3feef271b7a3f0..62fefbbaf263c5a6d73b56e4c876680cd2a8a1dc 100644 (file)
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -75,6 +75,7 @@ extern void si_init_uvd_internal_cg(struct radeon_device *rdev);
 extern int cik_sdma_resume(struct radeon_device *rdev);
 extern void cik_sdma_enable(struct radeon_device *rdev, bool enable);
 extern void cik_sdma_fini(struct radeon_device *rdev);
+extern void vce_v2_0_enable_mgcg(struct radeon_device *rdev, bool enable);
 static void cik_rlc_stop(struct radeon_device *rdev);
 static void cik_pcie_gen3_enable(struct radeon_device *rdev);
 static void cik_program_aspm(struct radeon_device *rdev);
@@ -2028,6 +2029,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
                                break;
                        case 5:
                                gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+                                                PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
                                break;
                        case 6:
@@ -2048,6 +2050,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
                                break;
                        case 9:
                                gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+                                                PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
                                break;
                        case 10:
@@ -2070,6 +2073,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
                                break;
                        case 13:
                                gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+                                                PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
                                break;
                        case 14:
@@ -2092,6 +2096,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
                                break;
                        case 27:
                                gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+                                                PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
                                break;
                        case 28:
@@ -2246,6 +2251,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
                                break;
                        case 5:
                                gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+                                                PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
                                break;
                        case 6:
@@ -2266,6 +2272,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
                                break;
                        case 9:
                                gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+                                                PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
                                break;
                        case 10:
@@ -2288,6 +2295,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
                                break;
                        case 13:
                                gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+                                                PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
                                break;
                        case 14:
@@ -2310,6 +2318,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
                                break;
                        case 27:
                                gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+                                                PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
                                break;
                        case 28:
@@ -2466,6 +2475,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
                                        break;
                                case 5:
                                        gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+                                                        PIPE_CONFIG(ADDR_SURF_P4_16x16) |
                                                         MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
                                        break;
                                case 6:
@@ -2486,6 +2496,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
                                        break;
                                case 9:
                                        gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+                                                        PIPE_CONFIG(ADDR_SURF_P4_16x16) |
                                                         MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
                                        break;
                                case 10:
@@ -2508,6 +2519,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
                                        break;
                                case 13:
                                        gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+                                                        PIPE_CONFIG(ADDR_SURF_P4_16x16) |
                                                         MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
                                        break;
                                case 14:
@@ -2530,6 +2542,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
                                        break;
                                case 27:
                                        gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+                                                        PIPE_CONFIG(ADDR_SURF_P4_16x16) |
                                                         MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
                                        break;
                                case 28:
@@ -2592,6 +2605,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
                                        break;
                                case 5:
                                        gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+                                                        PIPE_CONFIG(ADDR_SURF_P4_8x16) |
                                                         MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
                                        break;
                                case 6:
@@ -2612,6 +2626,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
                                        break;
                                case 9:
                                        gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+                                                        PIPE_CONFIG(ADDR_SURF_P4_8x16) |
                                                         MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
                                        break;
                                case 10:
@@ -2634,6 +2649,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
                                        break;
                                case 13:
                                        gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+                                                        PIPE_CONFIG(ADDR_SURF_P4_8x16) |
                                                         MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
                                        break;
                                case 14:
@@ -2656,6 +2672,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
                                        break;
                                case 27:
                                        gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+                                                        PIPE_CONFIG(ADDR_SURF_P4_8x16) |
                                                         MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
                                        break;
                                case 28:
@@ -2812,6 +2829,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
                                break;
                        case 5:
                                gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
                                break;
                        case 6:
@@ -2827,11 +2845,13 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
                                                 TILE_SPLIT(split_equal_to_row_size));
                                break;
                        case 8:
-                               gb_tile_moden = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
+                               gb_tile_moden = ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
+                                               PIPE_CONFIG(ADDR_SURF_P2);
                                break;
                        case 9:
                                gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-                                                MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
+                                                PIPE_CONFIG(ADDR_SURF_P2));
                                break;
                        case 10:
                                gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
@@ -2853,6 +2873,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
                                break;
                        case 13:
                                gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
                                break;
                        case 14:
@@ -2875,7 +2896,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
                                break;
                        case 27:
                                gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-                                                MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+                                                PIPE_CONFIG(ADDR_SURF_P2));
                                break;
                        case 28:
                                gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
@@ -4030,8 +4052,6 @@ static int cik_cp_gfx_resume(struct radeon_device *rdev)
        WREG32(CP_RB0_BASE, rb_addr);
        WREG32(CP_RB0_BASE_HI, upper_32_bits(rb_addr));
 
-       ring->rptr = RREG32(CP_RB0_RPTR);
-
        /* start the ring */
        cik_cp_gfx_start(rdev);
        rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
@@ -4134,8 +4154,11 @@ static void cik_cp_compute_enable(struct radeon_device *rdev, bool enable)
 {
        if (enable)
                WREG32(CP_MEC_CNTL, 0);
-       else
+       else {
                WREG32(CP_MEC_CNTL, (MEC_ME1_HALT | MEC_ME2_HALT));
+               rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
+               rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
+       }
        udelay(50);
 }
 
@@ -4586,8 +4609,7 @@ static int cik_cp_compute_resume(struct radeon_device *rdev)
                rdev->ring[idx].wptr = 0;
                mqd->queue_state.cp_hqd_pq_wptr = rdev->ring[idx].wptr;
                WREG32(CP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
-               rdev->ring[idx].rptr = RREG32(CP_HQD_PQ_RPTR);
-               mqd->queue_state.cp_hqd_pq_rptr = rdev->ring[idx].rptr;
+               mqd->queue_state.cp_hqd_pq_rptr = RREG32(CP_HQD_PQ_RPTR);
 
                /* set the vmid for the queue */
                mqd->queue_state.cp_hqd_vmid = 0;
@@ -5117,11 +5139,9 @@ bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
        if (!(reset_mask & (RADEON_RESET_GFX |
                            RADEON_RESET_COMPUTE |
                            RADEON_RESET_CP))) {
-               radeon_ring_lockup_update(ring);
+               radeon_ring_lockup_update(rdev, ring);
                return false;
        }
-       /* force CP activities */
-       radeon_ring_force_activity(rdev, ring);
        return radeon_ring_test_lockup(rdev, ring);
 }
 
@@ -6141,6 +6161,10 @@ void cik_update_cg(struct radeon_device *rdev,
                cik_enable_hdp_mgcg(rdev, enable);
                cik_enable_hdp_ls(rdev, enable);
        }
+
+       if (block & RADEON_CG_BLOCK_VCE) {
+               vce_v2_0_enable_mgcg(rdev, enable);
+       }
 }
 
 static void cik_init_cg(struct radeon_device *rdev)
@@ -7490,6 +7514,20 @@ restart_ih:
                        /* reset addr and status */
                        WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
                        break;
+               case 167: /* VCE */
+                       DRM_DEBUG("IH: VCE int: 0x%08x\n", src_data);
+                       switch (src_data) {
+                       case 0:
+                               radeon_fence_process(rdev, TN_RING_TYPE_VCE1_INDEX);
+                               break;
+                       case 1:
+                               radeon_fence_process(rdev, TN_RING_TYPE_VCE2_INDEX);
+                               break;
+                       default:
+                               DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
+                               break;
+                       }
+                       break;
                case 176: /* GFX RB CP_INT */
                case 177: /* GFX IB CP_INT */
                        radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
@@ -7789,6 +7827,22 @@ static int cik_startup(struct radeon_device *rdev)
        if (r)
                rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
 
+       r = radeon_vce_resume(rdev);
+       if (!r) {
+               r = vce_v2_0_resume(rdev);
+               if (!r)
+                       r = radeon_fence_driver_start_ring(rdev,
+                                                          TN_RING_TYPE_VCE1_INDEX);
+               if (!r)
+                       r = radeon_fence_driver_start_ring(rdev,
+                                                          TN_RING_TYPE_VCE2_INDEX);
+       }
+       if (r) {
+               dev_err(rdev->dev, "VCE init error (%d).\n", r);
+               rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size = 0;
+               rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_size = 0;
+       }
+
        /* Enable IRQ */
        if (!rdev->irq.installed) {
                r = radeon_irq_kms_init(rdev);
@@ -7864,6 +7918,23 @@ static int cik_startup(struct radeon_device *rdev)
                        DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
        }
 
+       r = -ENOENT;
+
+       ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];
+       if (ring->ring_size)
+               r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
+                                    VCE_CMD_NO_OP);
+
+       ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];
+       if (ring->ring_size)
+               r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
+                                    VCE_CMD_NO_OP);
+
+       if (!r)
+               r = vce_v1_0_init(rdev);
+       else if (r != -ENOENT)
+               DRM_ERROR("radeon: failed initializing VCE (%d).\n", r);
+
        r = radeon_ib_pool_init(rdev);
        if (r) {
                dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
@@ -7935,6 +8006,7 @@ int cik_suspend(struct radeon_device *rdev)
        cik_sdma_enable(rdev, false);
        uvd_v1_0_fini(rdev);
        radeon_uvd_suspend(rdev);
+       radeon_vce_suspend(rdev);
        cik_fini_pg(rdev);
        cik_fini_cg(rdev);
        cik_irq_suspend(rdev);
@@ -8067,6 +8139,17 @@ int cik_init(struct radeon_device *rdev)
                r600_ring_init(rdev, ring, 4096);
        }
 
+       r = radeon_vce_init(rdev);
+       if (!r) {
+               ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];
+               ring->ring_obj = NULL;
+               r600_ring_init(rdev, ring, 4096);
+
+               ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];
+               ring->ring_obj = NULL;
+               r600_ring_init(rdev, ring, 4096);
+       }
+
        rdev->ih.ring_obj = NULL;
        r600_ih_ring_init(rdev, 64 * 1024);
 
@@ -8128,6 +8211,7 @@ void cik_fini(struct radeon_device *rdev)
        radeon_irq_kms_fini(rdev);
        uvd_v1_0_fini(rdev);
        radeon_uvd_fini(rdev);
+       radeon_vce_fini(rdev);
        cik_pcie_gart_fini(rdev);
        r600_vram_scratch_fini(rdev);
        radeon_gem_fini(rdev);
@@ -8866,6 +8950,41 @@ int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
        return r;
 }
 
+int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk)
+{
+       int r, i;
+       struct atom_clock_dividers dividers;
+       u32 tmp;
+
+       r = radeon_atom_get_clock_dividers(rdev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
+                                          ecclk, false, &dividers);
+       if (r)
+               return r;
+
+       for (i = 0; i < 100; i++) {
+               if (RREG32_SMC(CG_ECLK_STATUS) & ECLK_STATUS)
+                       break;
+               mdelay(10);
+       }
+       if (i == 100)
+               return -ETIMEDOUT;
+
+       tmp = RREG32_SMC(CG_ECLK_CNTL);
+       tmp &= ~(ECLK_DIR_CNTL_EN|ECLK_DIVIDER_MASK);
+       tmp |= dividers.post_divider;
+       WREG32_SMC(CG_ECLK_CNTL, tmp);
+
+       for (i = 0; i < 100; i++) {
+               if (RREG32_SMC(CG_ECLK_STATUS) & ECLK_STATUS)
+                       break;
+               mdelay(10);
+       }
+       if (i == 100)
+               return -ETIMEDOUT;
+
+       return 0;
+}
+
 static void cik_pcie_gen3_enable(struct radeon_device *rdev)
 {
        struct pci_dev *root = rdev->pdev->bus->self;