Merge branch 'gpio/merge' of git://git.secretlab.ca/git/linux-2.6
[deliverable/linux.git] / drivers / gpu / drm / radeon / evergreen.c
index 86157b172c8844dc39e7ba8e4804723c4b98779a..a2d900809900638be0992b969fab327bacbd61c1 100644 (file)
@@ -88,7 +88,8 @@ u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
 /* get temperature in millidegrees */
 int evergreen_get_temp(struct radeon_device *rdev)
 {
-       u32 temp, toffset, actual_temp = 0;
+       u32 temp, toffset;
+       int actual_temp = 0;
 
        if (rdev->family == CHIP_JUNIPER) {
                toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
@@ -139,11 +140,17 @@ void evergreen_pm_misc(struct radeon_device *rdev)
        struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 
        if (voltage->type == VOLTAGE_SW) {
+               /* 0xff01 is a flag rather then an actual voltage */
+               if (voltage->voltage == 0xff01)
+                       return;
                if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
                        radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
                        rdev->pm.current_vddc = voltage->voltage;
                        DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
                }
+               /* 0xff01 is a flag rather then an actual voltage */
+               if (voltage->vddci == 0xff01)
+                       return;
                if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
                        radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
                        rdev->pm.current_vddci = voltage->vddci;
@@ -2006,9 +2013,9 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
                rdev->config.evergreen.tile_config |= (3 << 0);
                break;
        }
-       /* num banks is 8 on all fusion asics */
+       /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
        if (rdev->flags & RADEON_IS_IGP)
-               rdev->config.evergreen.tile_config |= 8 << 4;
+               rdev->config.evergreen.tile_config |= 1 << 4;
        else
                rdev->config.evergreen.tile_config |=
                        ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
@@ -2241,7 +2248,10 @@ int evergreen_mc_init(struct radeon_device *rdev)
 
        /* Get VRAM informations */
        rdev->mc.vram_is_ddr = true;
-       tmp = RREG32(MC_ARB_RAMCFG);
+       if (rdev->flags & RADEON_IS_IGP)
+               tmp = RREG32(FUS_MC_ARB_RAMCFG);
+       else
+               tmp = RREG32(MC_ARB_RAMCFG);
        if (tmp & CHANSIZE_OVERRIDE) {
                chansize = 16;
        } else if (tmp & CHANSIZE_MASK) {
@@ -2694,28 +2704,25 @@ static inline u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
 
 int evergreen_irq_process(struct radeon_device *rdev)
 {
-       u32 wptr = evergreen_get_ih_wptr(rdev);
-       u32 rptr = rdev->ih.rptr;
+       u32 wptr;
+       u32 rptr;
        u32 src_id, src_data;
        u32 ring_index;
        unsigned long flags;
        bool queue_hotplug = false;
 
-       DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
-       if (!rdev->ih.enabled)
+       if (!rdev->ih.enabled || rdev->shutdown)
                return IRQ_NONE;
 
-       spin_lock_irqsave(&rdev->ih.lock, flags);
+       wptr = evergreen_get_ih_wptr(rdev);
+       rptr = rdev->ih.rptr;
+       DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
 
+       spin_lock_irqsave(&rdev->ih.lock, flags);
        if (rptr == wptr) {
                spin_unlock_irqrestore(&rdev->ih.lock, flags);
                return IRQ_NONE;
        }
-       if (rdev->shutdown) {
-               spin_unlock_irqrestore(&rdev->ih.lock, flags);
-               return IRQ_NONE;
-       }
-
 restart_ih:
        /* display interrupts */
        evergreen_irq_ack(rdev);
@@ -3230,6 +3237,7 @@ void evergreen_fini(struct radeon_device *rdev)
        r700_cp_fini(rdev);
        r600_irq_fini(rdev);
        radeon_wb_fini(rdev);
+       radeon_ib_pool_fini(rdev);
        radeon_irq_kms_fini(rdev);
        evergreen_pcie_gart_fini(rdev);
        radeon_gem_fini(rdev);
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