drm/radeon/kms: skip cb/db checking if SX_MISC is 1 on r600+

[deliverable/linux.git] / drivers / gpu / drm / radeon / evergreen_cs.c

diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c
index 49203b67b81b23eb99f514032f02724f41213f9e..8bf576a50c5657d8ecdcbae2a594044de16e4313 100644 (file)
--- a/drivers/gpu/drm/radeon/evergreen_cs.c
+++ b/drivers/gpu/drm/radeon/evergreen_cs.c
@@ -85,6 +85,7 @@ struct evergreen_cs_track {
        u32                     db_s_write_offset;
        struct radeon_bo        *db_s_read_bo;
        struct radeon_bo        *db_s_write_bo;
+       bool                    sx_misc_kill_all_prims;
 };
 
 static u32 evergreen_cs_get_aray_mode(u32 tiling_flags)
@@ -162,6 +163,7 @@ static void evergreen_cs_track_init(struct evergreen_cs_track *track)
                track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF;
                track->vgt_strmout_bo_mc[i] = 0xFFFFFFFF;
        }
+       track->sx_misc_kill_all_prims = false;
 }
 
 struct eg_surface {
@@ -821,6 +823,9 @@ static int evergreen_cs_track_check(struct radeon_cs_parser *p)
                }
        }
 
+       if (track->sx_misc_kill_all_prims)
+               return 0;
+
        /* check that we have a cb for each enabled target
         */
        tmp = track->cb_target_mask;
@@ -1748,6 +1753,9 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                }
                ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
                break;
+       case SX_MISC:
+               track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0;
+               break;
        default:
                dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
                return -EINVAL;