Merge tag 'v3.14' into drm-intel-next-queued

[deliverable/linux.git] / drivers / gpu / drm / radeon / r100.c

diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index ef024ce3f7ccfd39b1be47be9840a401b588b1dc..030f8e49c5ee18513cd061897639a991ce06dfad 100644 (file)
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -1193,7 +1193,6 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
 
        WREG32(RADEON_CP_RB_CNTL, tmp);
        udelay(10);
-       ring->rptr = RREG32(RADEON_CP_RB_RPTR);
        /* Set cp mode to bus mastering & enable cp*/
        WREG32(RADEON_CP_CSQ_MODE,
               REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
@@ -1275,12 +1274,12 @@ int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
 
        value = radeon_get_ib_value(p, idx);
        tmp = value & 0x003fffff;
-       tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
+       tmp += (((u32)reloc->gpu_offset) >> 10);
 
        if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
-               if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
+               if (reloc->tiling_flags & RADEON_TILING_MACRO)
                        tile_flags |= RADEON_DST_TILE_MACRO;
-               if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
+               if (reloc->tiling_flags & RADEON_TILING_MICRO) {
                        if (reg == RADEON_SRC_PITCH_OFFSET) {
                                DRM_ERROR("Cannot src blit from microtiled surface\n");
                                radeon_cs_dump_packet(p, pkt);
@@ -1326,7 +1325,7 @@ int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
                        return r;
                }
                idx_value = radeon_get_ib_value(p, idx);
-               ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
+               ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
 
                track->arrays[i + 0].esize = idx_value >> 8;
                track->arrays[i + 0].robj = reloc->robj;
@@ -1338,7 +1337,7 @@ int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
                        radeon_cs_dump_packet(p, pkt);
                        return r;
                }
-               ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
+               ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset);
                track->arrays[i + 1].robj = reloc->robj;
                track->arrays[i + 1].esize = idx_value >> 24;
                track->arrays[i + 1].esize &= 0x7F;
@@ -1352,7 +1351,7 @@ int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
                        return r;
                }
                idx_value = radeon_get_ib_value(p, idx);
-               ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
+               ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
                track->arrays[i + 0].robj = reloc->robj;
                track->arrays[i + 0].esize = idx_value >> 8;
                track->arrays[i + 0].esize &= 0x7F;
@@ -1595,7 +1594,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
                track->zb.robj = reloc->robj;
                track->zb.offset = idx_value;
                track->zb_dirty = true;
-               ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
+               ib[idx] = idx_value + ((u32)reloc->gpu_offset);
                break;
        case RADEON_RB3D_COLOROFFSET:
                r = radeon_cs_packet_next_reloc(p, &reloc, 0);
@@ -1608,7 +1607,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
                track->cb[0].robj = reloc->robj;
                track->cb[0].offset = idx_value;
                track->cb_dirty = true;
-               ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
+               ib[idx] = idx_value + ((u32)reloc->gpu_offset);
                break;
        case RADEON_PP_TXOFFSET_0:
        case RADEON_PP_TXOFFSET_1:
@@ -1622,16 +1621,16 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
                        return r;
                }
                if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
-                       if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
+                       if (reloc->tiling_flags & RADEON_TILING_MACRO)
                                tile_flags |= RADEON_TXO_MACRO_TILE;
-                       if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
+                       if (reloc->tiling_flags & RADEON_TILING_MICRO)
                                tile_flags |= RADEON_TXO_MICRO_TILE_X2;
 
                        tmp = idx_value & ~(0x7 << 2);
                        tmp |= tile_flags;
-                       ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset);
+                       ib[idx] = tmp + ((u32)reloc->gpu_offset);
                } else
-                       ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
+                       ib[idx] = idx_value + ((u32)reloc->gpu_offset);
                track->textures[i].robj = reloc->robj;
                track->tex_dirty = true;
                break;
@@ -1649,7 +1648,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
                        return r;
                }
                track->textures[0].cube_info[i].offset = idx_value;
-               ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
+               ib[idx] = idx_value + ((u32)reloc->gpu_offset);
                track->textures[0].cube_info[i].robj = reloc->robj;
                track->tex_dirty = true;
                break;
@@ -1667,7 +1666,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
                        return r;
                }
                track->textures[1].cube_info[i].offset = idx_value;
-               ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
+               ib[idx] = idx_value + ((u32)reloc->gpu_offset);
                track->textures[1].cube_info[i].robj = reloc->robj;
                track->tex_dirty = true;
                break;
@@ -1685,7 +1684,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
                        return r;
                }
                track->textures[2].cube_info[i].offset = idx_value;
-               ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
+               ib[idx] = idx_value + ((u32)reloc->gpu_offset);
                track->textures[2].cube_info[i].robj = reloc->robj;
                track->tex_dirty = true;
                break;
@@ -1703,9 +1702,9 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
                        return r;
                }
                if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
-                       if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
+                       if (reloc->tiling_flags & RADEON_TILING_MACRO)
                                tile_flags |= RADEON_COLOR_TILE_ENABLE;
-                       if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
+                       if (reloc->tiling_flags & RADEON_TILING_MICRO)
                                tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
 
                        tmp = idx_value & ~(0x7 << 16);
@@ -1773,7 +1772,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
                        radeon_cs_dump_packet(p, pkt);
                        return r;
                }
-               ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
+               ib[idx] = idx_value + ((u32)reloc->gpu_offset);
                break;
        case RADEON_PP_CNTL:
                {
@@ -1933,7 +1932,7 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
                        radeon_cs_dump_packet(p, pkt);
                        return r;
                }
-               ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
+               ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset);
                r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
                if (r) {
                        return r;
@@ -1947,7 +1946,7 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
                        radeon_cs_dump_packet(p, pkt);
                        return r;
                }
-               ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
+               ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset);
                track->num_arrays = 1;
                track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
 
@@ -2523,11 +2522,9 @@ bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
 
        rbbm_status = RREG32(R_000E40_RBBM_STATUS);
        if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
-               radeon_ring_lockup_update(ring);
+               radeon_ring_lockup_update(rdev, ring);
                return false;
        }
-       /* force CP activities */
-       radeon_ring_force_activity(rdev, ring);
        return radeon_ring_test_lockup(rdev, ring);
 }
 
@@ -3942,8 +3939,6 @@ int r100_resume(struct radeon_device *rdev)
        /* Initialize surface registers */
        radeon_surface_init(rdev);
 
-       radeon_pm_resume(rdev);
-
        rdev->accel_working = true;
        r = r100_startup(rdev);
        if (r) {