drm/radeon/kms: add initial Evergreen support (Radeon HD 5xxx)

[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h

diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 53468680de70588100888e477ed3c887c5322bbe..a7a96a2408440052cde6c43aa905764a6c34592d 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -138,11 +138,14 @@ void radeon_dummy_page_fini(struct radeon_device *rdev);
 struct radeon_clock {
        struct radeon_pll p1pll;
        struct radeon_pll p2pll;
+       struct radeon_pll dcpll;
        struct radeon_pll spll;
        struct radeon_pll mpll;
        /* 10 Khz units */
        uint32_t default_mclk;
        uint32_t default_sclk;
+       uint32_t default_dispclk;
+       uint32_t dp_extclk;
 };
 
 /*
@@ -351,6 +354,7 @@ struct radeon_irq {
        bool            sw_int;
        /* FIXME: use a define max crtc rather than hardcode it */
        bool            crtc_vblank_int[2];
+       wait_queue_head_t       vblank_queue;
        /* FIXME: use defines for max hpd/dacs */
        bool            hpd[6];
        spinlock_t sw_lock;
@@ -382,6 +386,7 @@ struct radeon_ib_pool {
        struct mutex            mutex;
        struct radeon_bo        *robj;
        struct list_head        scheduled_ibs;
+       struct list_head        bogus_ib;
        struct radeon_ib        ibs[RADEON_IB_POOL_SIZE];
        bool                    ready;
        DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
@@ -436,6 +441,7 @@ int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
 int radeon_ib_pool_init(struct radeon_device *rdev);
 void radeon_ib_pool_fini(struct radeon_device *rdev);
 int radeon_ib_test(struct radeon_device *rdev);
+extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
 /* Ring access between begin & end cannot sleep */
 void radeon_ring_free_size(struct radeon_device *rdev);
 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
@@ -601,6 +607,13 @@ enum radeon_pm_state_type {
        POWER_STATE_TYPE_PERFORMANCE,
 };
 
+enum radeon_pm_clock_mode_type {
+       POWER_MODE_TYPE_DEFAULT,
+       POWER_MODE_TYPE_LOW,
+       POWER_MODE_TYPE_MID,
+       POWER_MODE_TYPE_HIGH,
+};
+
 struct radeon_voltage {
        enum radeon_voltage_type type;
        /* gpio voltage */
@@ -641,6 +654,7 @@ struct radeon_power_state {
        int num_clock_modes;
        /* currently selected clock mode */
        struct radeon_pm_clock_info *current_clock_mode;
+       struct radeon_pm_clock_info *requested_clock_mode;
        struct radeon_pm_clock_info *default_clock_mode;
        /* non clock info about this state */
        struct radeon_pm_non_clock_info non_clock_info;
@@ -649,19 +663,13 @@ struct radeon_power_state {
 
 struct radeon_pm {
        struct mutex            mutex;
-       struct work_struct      reclock_work;
        struct delayed_work     idle_work;
        enum radeon_pm_state    state;
        enum radeon_pm_action   planned_action;
        unsigned long           action_timeout;
        bool                    downclocked;
-       bool                    vblank_callback;
        int                     active_crtcs;
        int                     req_vblank;
-       uint32_t                min_gpu_engine_clock;
-       uint32_t                min_gpu_memory_clock;
-       uint32_t                min_mode_engine_clock;
-       uint32_t                min_mode_memory_clock;
        fixed20_12              max_bandwidth;
        fixed20_12              igp_sideport_mclk;
        fixed20_12              igp_system_mclk;
@@ -678,6 +686,7 @@ struct radeon_pm {
        /* number of valid power states */
        int                     num_power_states;
        struct radeon_power_state *current_power_state;
+       struct radeon_power_state *requested_power_state;
        struct radeon_power_state *default_power_state;
 };
 
@@ -1056,7 +1065,7 @@ void r100_pll_errata_after_index(struct radeon_device *rdev);
 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
-
+#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
 
 /*
  * BIOS helpers.
@@ -1290,6 +1299,14 @@ extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder,
                                            uint8_t status_bits,
                                            uint8_t category_code);
 
+/* evergreen */
+struct evergreen_mc_save {
+       u32 vga_control[6];
+       u32 vga_render_control;
+       u32 vga_hdp_control;
+       u32 crtc_control[6];
+};
+
 #include "radeon_object.h"
 
 #endif