#include "iwl-eeprom.h"
#include "iwl-core.h"
#include "iwl-4965.h"
+#include "iwl-io.h"
#include "iwl-helpers.h"
+/* module parameters */
+static struct iwl_mod_params iwl4965_mod_params = {
+ .num_of_queues = IWL_MAX_NUM_QUEUES,
+ .enable_qos = 1,
+ .amsdu_size_8K = 1,
+ /* the rest are 0 by default */
+};
+
static void iwl4965_hw_card_show_info(struct iwl_priv *priv);
#define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
int ret;
int i;
- priv->antenna = (enum iwl4965_antenna)iwl4965_mod_params.antenna;
+ priv->antenna = (enum iwl4965_antenna)priv->cfg->mod_params->antenna;
priv->retry_rate = 1;
priv->ibss_beacon = NULL;
unsigned long flags;
spin_lock_irqsave(&priv->lock, flags);
- rc = iwl4965_grab_nic_access(priv);
+ rc = iwl_grab_nic_access(priv);
if (rc) {
spin_unlock_irqrestore(&priv->lock, flags);
return rc;
}
/* stop Rx DMA */
- iwl4965_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
- rc = iwl4965_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
+ iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
+ rc = iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
(1 << 24), 1000);
if (rc < 0)
IWL_ERROR("Can't stop Rx DMA.\n");
- iwl4965_release_nic_access(priv);
+ iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
return 0;
unsigned long flags;
spin_lock_irqsave(&priv->lock, flags);
- ret = iwl4965_grab_nic_access(priv);
+ ret = iwl_grab_nic_access(priv);
if (ret) {
spin_unlock_irqrestore(&priv->lock, flags);
return ret;
&val);
if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT)
- iwl4965_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
+ iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
~APMG_PS_CTRL_MSK_PWR_SRC);
} else
- iwl4965_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
+ iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
~APMG_PS_CTRL_MSK_PWR_SRC);
- iwl4965_release_nic_access(priv);
+ iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
return ret;
unsigned int rb_size;
spin_lock_irqsave(&priv->lock, flags);
- rc = iwl4965_grab_nic_access(priv);
+ rc = iwl_grab_nic_access(priv);
if (rc) {
spin_unlock_irqrestore(&priv->lock, flags);
return rc;
}
- if (iwl4965_mod_params.amsdu_size_8K)
+ if (priv->cfg->mod_params->amsdu_size_8K)
rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
else
rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
/* Stop Rx DMA */
- iwl4965_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
+ iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
/* Reset driver's Rx queue write index */
- iwl4965_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
+ iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
/* Tell device where to find RBD circular buffer in DRAM */
- iwl4965_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
- rxq->dma_addr >> 8);
+ iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
+ rxq->dma_addr >> 8);
/* Tell device where in DRAM to update its Rx status */
- iwl4965_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
- (priv->hw_setting.shared_phys +
- offsetof(struct iwl4965_shared, val0)) >> 4);
+ iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
+ (priv->hw_setting.shared_phys +
+ offsetof(struct iwl4965_shared, val0)) >> 4);
/* Enable Rx DMA, enable host interrupt, Rx buffer size 4k, 256 RBDs */
- iwl4965_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
- FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
- FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
- rb_size |
+ iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
+ FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
+ FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
+ rb_size |
/*0x10 << 4 | */
- (RX_QUEUE_SIZE_LOG <<
+ (RX_QUEUE_SIZE_LOG <<
FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT));
/*
- * iwl4965_write32(priv,CSR_INT_COAL_REG,0);
+ * iwl_write32(priv,CSR_INT_COAL_REG,0);
*/
- iwl4965_release_nic_access(priv);
+ iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
return 0;
int rc;
spin_lock_irqsave(&priv->lock, flags);
- rc = iwl4965_grab_nic_access(priv);
+ rc = iwl_grab_nic_access(priv);
if (rc)
goto out;
- iwl4965_write_direct32(priv, IWL_FH_KW_MEM_ADDR_REG,
+ iwl_write_direct32(priv, IWL_FH_KW_MEM_ADDR_REG,
priv->kw.dma_addr >> 4);
- iwl4965_release_nic_access(priv);
+ iwl_release_nic_access(priv);
out:
spin_unlock_irqrestore(&priv->lock, flags);
return rc;
spin_lock_irqsave(&priv->lock, flags);
- rc = iwl4965_grab_nic_access(priv);
+ rc = iwl_grab_nic_access(priv);
if (unlikely(rc)) {
IWL_ERROR("TX reset failed");
spin_unlock_irqrestore(&priv->lock, flags);
}
/* Turn off all Tx DMA channels */
- iwl4965_write_prph(priv, KDR_SCD_TXFACT, 0);
- iwl4965_release_nic_access(priv);
+ iwl_write_prph(priv, KDR_SCD_TXFACT, 0);
+ iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
/* Tell 4965 where to find the keep-warm buffer */
/* nic_init */
spin_lock_irqsave(&priv->lock, flags);
- iwl4965_set_bit(priv, CSR_GIO_CHICKEN_BITS,
+ iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
- iwl4965_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
- rc = iwl4965_poll_bit(priv, CSR_GP_CNTRL,
+ iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
+ rc = iwl_poll_bit(priv, CSR_GP_CNTRL,
CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
if (rc < 0) {
return rc;
}
- rc = iwl4965_grab_nic_access(priv);
+ rc = iwl_grab_nic_access(priv);
if (rc) {
spin_unlock_irqrestore(&priv->lock, flags);
return rc;
}
- iwl4965_read_prph(priv, APMG_CLK_CTRL_REG);
+ iwl_read_prph(priv, APMG_CLK_CTRL_REG);
- iwl4965_write_prph(priv, APMG_CLK_CTRL_REG,
- APMG_CLK_VAL_DMA_CLK_RQT |
- APMG_CLK_VAL_BSM_CLK_RQT);
- iwl4965_read_prph(priv, APMG_CLK_CTRL_REG);
+ iwl_write_prph(priv, APMG_CLK_CTRL_REG,
+ APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
+ iwl_read_prph(priv, APMG_CLK_CTRL_REG);
udelay(20);
- iwl4965_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
- APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
+ iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
+ APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
- iwl4965_release_nic_access(priv);
- iwl4965_write32(priv, CSR_INT_COALESCING, 512 / 32);
+ iwl_release_nic_access(priv);
+ iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
spin_unlock_irqrestore(&priv->lock, flags);
/* Determine HW type */
/* set CSR_HW_CONFIG_REG for uCode use */
- iwl4965_set_bit(priv, CSR_HW_IF_CONFIG_REG,
- CSR49_HW_IF_CONFIG_REG_BIT_4965_R |
- CSR49_HW_IF_CONFIG_REG_BIT_RADIO_SI |
- CSR49_HW_IF_CONFIG_REG_BIT_MAC_SI);
+ iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
+ CSR49_HW_IF_CONFIG_REG_BIT_4965_R |
+ CSR49_HW_IF_CONFIG_REG_BIT_RADIO_SI |
+ CSR49_HW_IF_CONFIG_REG_BIT_MAC_SI);
- rc = iwl4965_grab_nic_access(priv);
+ rc = iwl_grab_nic_access(priv);
if (rc < 0) {
spin_unlock_irqrestore(&priv->lock, flags);
IWL_DEBUG_INFO("Failed to init the card\n");
return rc;
}
- iwl4965_read_prph(priv, APMG_PS_CTRL_REG);
- iwl4965_set_bits_prph(priv, APMG_PS_CTRL_REG,
- APMG_PS_CTRL_VAL_RESET_REQ);
+ iwl_read_prph(priv, APMG_PS_CTRL_REG);
+ iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
udelay(5);
- iwl4965_clear_bits_prph(priv, APMG_PS_CTRL_REG,
- APMG_PS_CTRL_VAL_RESET_REQ);
+ iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
- iwl4965_release_nic_access(priv);
+ iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
iwl4965_hw_card_show_info(priv);
spin_lock_irqsave(&priv->lock, flags);
/* set stop master bit */
- iwl4965_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
+ iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
- reg_val = iwl4965_read32(priv, CSR_GP_CNTRL);
+ reg_val = iwl_read32(priv, CSR_GP_CNTRL);
if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
(reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
IWL_DEBUG_INFO("Card in power save, master is already "
"stopped\n");
else {
- rc = iwl4965_poll_bit(priv, CSR_RESET,
+ rc = iwl_poll_bit(priv, CSR_RESET,
CSR_RESET_REG_FLAG_MASTER_DISABLED,
CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
if (rc < 0) {
/* Stop each Tx DMA channel, and wait for it to be idle */
for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++) {
spin_lock_irqsave(&priv->lock, flags);
- if (iwl4965_grab_nic_access(priv)) {
+ if (iwl_grab_nic_access(priv)) {
spin_unlock_irqrestore(&priv->lock, flags);
continue;
}
- iwl4965_write_direct32(priv,
- IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
- 0x0);
- iwl4965_poll_direct_bit(priv, IWL_FH_TSSR_TX_STATUS_REG,
- IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
- (txq_id), 200);
- iwl4965_release_nic_access(priv);
+ iwl_write_direct32(priv,
+ IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 0x0);
+ iwl_poll_direct_bit(priv, IWL_FH_TSSR_TX_STATUS_REG,
+ IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
+ (txq_id), 200);
+ iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
}
spin_lock_irqsave(&priv->lock, flags);
- iwl4965_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
+ iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
udelay(10);
- iwl4965_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
- rc = iwl4965_poll_bit(priv, CSR_RESET,
+ iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
+ rc = iwl_poll_bit(priv, CSR_RESET,
CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);
udelay(10);
- rc = iwl4965_grab_nic_access(priv);
+ rc = iwl_grab_nic_access(priv);
if (!rc) {
- iwl4965_write_prph(priv, APMG_CLK_EN_REG,
- APMG_CLK_VAL_DMA_CLK_RQT |
- APMG_CLK_VAL_BSM_CLK_RQT);
+ iwl_write_prph(priv, APMG_CLK_EN_REG,
+ APMG_CLK_VAL_DMA_CLK_RQT |
+ APMG_CLK_VAL_BSM_CLK_RQT);
udelay(10);
- iwl4965_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
- APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
+ iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
+ APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
- iwl4965_release_nic_access(priv);
+ iwl_release_nic_access(priv);
}
clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
u32 temp_th;
u32 crit_temperature;
unsigned long flags;
- int rc = 0;
+ int ret = 0;
spin_lock_irqsave(&priv->lock, flags);
- iwl4965_write32(priv, CSR_UCODE_DRV_GP1_CLR,
+ iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
spin_unlock_irqrestore(&priv->lock, flags);
crit_temperature = ((temp_th * (R3-R1))/CT_LIMIT_CONST) + R2;
cmd.critical_temperature_R = cpu_to_le32(crit_temperature);
- rc = iwl4965_send_cmd_pdu(priv,
- REPLY_CT_KILL_CONFIG_CMD, sizeof(cmd), &cmd);
- if (rc)
+ ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
+ sizeof(cmd), &cmd);
+ if (ret)
IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
else
IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded\n");
}
static int iwl4965_sensitivity_callback(struct iwl_priv *priv,
- struct iwl4965_cmd *cmd, struct sk_buff *skb)
+ struct iwl_cmd *cmd, struct sk_buff *skb)
{
/* We didn't cache the SKB; let the caller free it */
return 1;
/* Prepare a SENSITIVITY_CMD, send to uCode if values have changed */
static int iwl4965_sensitivity_write(struct iwl_priv *priv, u8 flags)
{
- int rc = 0;
struct iwl4965_sensitivity_cmd cmd ;
struct iwl4965_sensitivity_data *data = NULL;
- struct iwl4965_host_cmd cmd_out = {
+ struct iwl_host_cmd cmd_out = {
.id = SENSITIVITY_CMD,
.len = sizeof(struct iwl4965_sensitivity_cmd),
.meta.flags = flags,
.data = &cmd,
};
+ int ret;
data = &(priv->sensitivity_data);
memcpy(&(priv->sensitivity_tbl[0]), &(cmd.table[0]),
sizeof(u16)*HD_TABLE_SIZE);
- rc = iwl4965_send_cmd(priv, &cmd_out);
- if (!rc) {
- IWL_DEBUG_CALIB("SENSITIVITY_CMD succeeded\n");
- return rc;
- }
+ ret = iwl_send_cmd(priv, &cmd_out);
+ if (ret)
+ IWL_ERROR("SENSITIVITY_CMD failed\n");
- return 0;
+ return ret;
}
void iwl4965_init_sensitivity(struct iwl_priv *priv, u8 flags, u8 force)
{
- int rc = 0;
- int i;
struct iwl4965_sensitivity_data *data = NULL;
+ int i;
+ int ret = 0;
IWL_DEBUG_CALIB("Start iwl4965_init_sensitivity\n");
memset(&(priv->sensitivity_tbl[0]), 0,
sizeof(u16)*HD_TABLE_SIZE);
- rc |= iwl4965_sensitivity_write(priv, flags);
- IWL_DEBUG_CALIB("<<return 0x%X\n", rc);
+ ret |= iwl4965_sensitivity_write(priv, flags);
+ IWL_DEBUG_CALIB("<<return 0x%X\n", ret);
return;
}
void iwl4965_chain_noise_reset(struct iwl_priv *priv)
{
struct iwl4965_chain_noise_data *data = NULL;
- int rc = 0;
data = &(priv->chain_noise_data);
if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl4965_is_associated(priv)) {
cmd.diff_gain_a = 0;
cmd.diff_gain_b = 0;
cmd.diff_gain_c = 0;
- rc = iwl4965_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
+ iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
sizeof(cmd), &cmd);
msleep(4);
data->state = IWL_CHAIN_NOISE_ACCUMULATE;
struct iwl4965_notif_statistics *stat_resp)
{
struct iwl4965_chain_noise_data *data = NULL;
- int rc = 0;
+ int ret = 0;
u32 chain_noise_a;
u32 chain_noise_b;
cmd.diff_gain_a = data->delta_gain_code[0];
cmd.diff_gain_b = data->delta_gain_code[1];
cmd.diff_gain_c = data->delta_gain_code[2];
- rc = iwl4965_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
+ ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
sizeof(cmd), &cmd);
- if (rc)
+ if (ret)
IWL_DEBUG_CALIB("fail sending cmd "
"REPLY_PHY_CALIBRATION_CMD \n");
static void iwl4965_sensitivity_calibration(struct iwl_priv *priv,
struct iwl4965_notif_statistics *resp)
{
- int rc = 0;
u32 rx_enable_time;
u32 fa_cck;
u32 fa_ofdm;
struct statistics_rx *statistics = &(resp->rx);
unsigned long flags;
struct statistics_general_data statis;
+ int ret;
data = &(priv->sensitivity_data);
iwl4965_sens_auto_corr_ofdm(priv, norm_fa_ofdm, rx_enable_time);
iwl4965_sens_energy_cck(priv, norm_fa_cck, rx_enable_time, &statis);
- rc |= iwl4965_sensitivity_write(priv, CMD_ASYNC);
+ ret = iwl4965_sensitivity_write(priv, CMD_ASYNC);
return;
}
*/
static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
{
- iwl4965_write_direct32(priv, HBUS_TARG_WRPTR,
+ iwl_write_direct32(priv, HBUS_TARG_WRPTR,
(index & 0xff) | (txq_id << 8));
- iwl4965_write_prph(priv, KDR_SCD_QUEUE_RDPTR(txq_id), index);
+ iwl_write_prph(priv, KDR_SCD_QUEUE_RDPTR(txq_id), index);
}
/**
int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
/* Set up and activate */
- iwl4965_write_prph(priv, KDR_SCD_QUEUE_STATUS_BITS(txq_id),
+ iwl_write_prph(priv, KDR_SCD_QUEUE_STATUS_BITS(txq_id),
(active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
(tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
(scd_retry << SCD_QUEUE_STTS_REG_POS_WSL) |
u32 a;
int i = 0;
unsigned long flags;
- int rc;
+ int ret;
spin_lock_irqsave(&priv->lock, flags);
priv->chain_noise_data.delta_gain_code[i] =
CHAIN_NOISE_DELTA_GAIN_INIT_VAL;
#endif /* CONFIG_IWL4965_SENSITIVITY*/
- rc = iwl4965_grab_nic_access(priv);
- if (rc) {
+ ret = iwl_grab_nic_access(priv);
+ if (ret) {
spin_unlock_irqrestore(&priv->lock, flags);
- return rc;
+ return ret;
}
/* Clear 4965's internal Tx Scheduler data base */
- priv->scd_base_addr = iwl4965_read_prph(priv, KDR_SCD_SRAM_BASE_ADDR);
+ priv->scd_base_addr = iwl_read_prph(priv, KDR_SCD_SRAM_BASE_ADDR);
a = priv->scd_base_addr + SCD_CONTEXT_DATA_OFFSET;
for (; a < priv->scd_base_addr + SCD_TX_STTS_BITMAP_OFFSET; a += 4)
- iwl4965_write_targ_mem(priv, a, 0);
+ iwl_write_targ_mem(priv, a, 0);
for (; a < priv->scd_base_addr + SCD_TRANSLATE_TBL_OFFSET; a += 4)
- iwl4965_write_targ_mem(priv, a, 0);
+ iwl_write_targ_mem(priv, a, 0);
for (; a < sizeof(u16) * priv->hw_setting.max_txq_num; a += 4)
- iwl4965_write_targ_mem(priv, a, 0);
+ iwl_write_targ_mem(priv, a, 0);
/* Tel 4965 where to find Tx byte count tables */
- iwl4965_write_prph(priv, KDR_SCD_DRAM_BASE_ADDR,
+ iwl_write_prph(priv, KDR_SCD_DRAM_BASE_ADDR,
(priv->hw_setting.shared_phys +
offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10);
/* Disable chain mode for all queues */
- iwl4965_write_prph(priv, KDR_SCD_QUEUECHAIN_SEL, 0);
+ iwl_write_prph(priv, KDR_SCD_QUEUECHAIN_SEL, 0);
/* Initialize each Tx queue (including the command queue) */
for (i = 0; i < priv->hw_setting.max_txq_num; i++) {
/* TFD circular buffer read/write indexes */
- iwl4965_write_prph(priv, KDR_SCD_QUEUE_RDPTR(i), 0);
- iwl4965_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
+ iwl_write_prph(priv, KDR_SCD_QUEUE_RDPTR(i), 0);
+ iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
/* Max Tx Window size for Scheduler-ACK mode */
- iwl4965_write_targ_mem(priv, priv->scd_base_addr +
+ iwl_write_targ_mem(priv, priv->scd_base_addr +
SCD_CONTEXT_QUEUE_OFFSET(i),
(SCD_WIN_SIZE <<
SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
/* Frame limit */
- iwl4965_write_targ_mem(priv, priv->scd_base_addr +
+ iwl_write_targ_mem(priv, priv->scd_base_addr +
SCD_CONTEXT_QUEUE_OFFSET(i) +
sizeof(u32),
(SCD_FRAME_LIMIT <<
SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
}
- iwl4965_write_prph(priv, KDR_SCD_INTERRUPT_MASK,
+ iwl_write_prph(priv, KDR_SCD_INTERRUPT_MASK,
(1 << priv->hw_setting.max_txq_num) - 1);
/* Activate all Tx DMA/FIFO channels */
- iwl4965_write_prph(priv, KDR_SCD_TXFACT,
+ iwl_write_prph(priv, KDR_SCD_TXFACT,
SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
}
- iwl4965_release_nic_access(priv);
+ iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
- return 0;
+ return ret;
}
/**
{
int ret = 0;
- if ((iwl4965_mod_params.num_of_queues > IWL_MAX_NUM_QUEUES) ||
- (iwl4965_mod_params.num_of_queues < IWL_MIN_NUM_QUEUES)) {
+ if ((priv->cfg->mod_params->num_of_queues > IWL_MAX_NUM_QUEUES) ||
+ (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
IWL_ERROR("invalid queues_num, should be between %d and %d\n",
IWL_MIN_NUM_QUEUES, IWL_MAX_NUM_QUEUES);
ret = -EINVAL;
memset(priv->hw_setting.shared_virt, 0, sizeof(struct iwl4965_shared));
- priv->hw_setting.max_txq_num = iwl4965_mod_params.num_of_queues;
+ priv->hw_setting.max_txq_num = priv->cfg->mod_params->num_of_queues;
priv->hw_setting.tx_cmd_len = sizeof(struct iwl4965_tx_cmd);
priv->hw_setting.max_rxq_size = RX_QUEUE_SIZE;
priv->hw_setting.max_rxq_log = RX_QUEUE_SIZE_LOG;
- if (iwl4965_mod_params.amsdu_size_8K)
+ if (priv->cfg->mod_params->amsdu_size_8K)
priv->hw_setting.rx_buf_size = IWL_RX_BUF_SIZE_8K;
else
priv->hw_setting.rx_buf_size = IWL_RX_BUF_SIZE_4K;
{
const struct iwl_channel_info *ch_info;
- ch_info = iwl4965_get_channel_info(priv, band, channel);
+ ch_info = iwl_get_channel_info(priv, band, channel);
if (!is_channel_valid(ch_info))
return NULL;
int iwl4965_hw_reg_send_txpower(struct iwl_priv *priv)
{
struct iwl4965_txpowertable_cmd cmd = { 0 };
- int rc = 0;
+ int ret;
u8 band = 0;
u8 is_fat = 0;
u8 ctrl_chan_high = 0;
cmd.band = band;
cmd.channel = priv->active_rxon.channel;
- rc = iwl4965_fill_txpower_tbl(priv, band,
+ ret = iwl4965_fill_txpower_tbl(priv, band,
le16_to_cpu(priv->active_rxon.channel),
is_fat, ctrl_chan_high, &cmd.tx_power);
- if (rc)
- return rc;
+ if (ret)
+ goto out;
- rc = iwl4965_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
- return rc;
+ ret = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
+
+out:
+ return ret;
}
int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
band = priv->band == IEEE80211_BAND_2GHZ;
- ch_info = iwl4965_get_channel_info(priv, priv->band, channel);
+ ch_info = iwl_get_channel_info(priv, priv->band, channel);
is_fat = is_fat_channel(priv->staging_rxon.flags);
return rc;
}
- rc = iwl4965_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
+ rc = iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
return rc;
}
#define RTS_DFAULT_RETRY_LIMIT 60
void iwl4965_hw_build_tx_cmd_rate(struct iwl_priv *priv,
- struct iwl4965_cmd *cmd,
+ struct iwl_cmd *cmd,
struct ieee80211_tx_control *ctrl,
struct ieee80211_hdr *hdr, int sta_id,
int is_hcca)
int txq_id = txq->q.id;
spin_lock_irqsave(&priv->lock, flags);
- rc = iwl4965_grab_nic_access(priv);
+ rc = iwl_grab_nic_access(priv);
if (rc) {
spin_unlock_irqrestore(&priv->lock, flags);
return rc;
}
/* Circular buffer (TFD queue in DRAM) physical base address */
- iwl4965_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
+ iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
txq->q.dma_addr >> 8);
/* Enable DMA channel, using same id as for TFD queue */
- iwl4965_write_direct32(
+ iwl_write_direct32(
priv, IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
- iwl4965_release_nic_access(priv);
+ iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
return 0;
#endif
}
+ iwl_leds_background(priv);
+
/* If the hardware hasn't reported a change in
* temperature then don't bother computing a
* calibrated temperature value */
stats->flag = 0;
hdr = (struct ieee80211_hdr *)rxb->skb->data;
- if (iwl4965_mod_params.hw_crypto)
+ if (priv->cfg->mod_params->hw_crypto)
iwl4965_set_decrypted_flag(priv, rxb->skb, ampdu_status, stats);
if (priv->add_radiotap)
ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
priv->alloc_rxb_skb--;
rxb->skb = NULL;
-#ifdef LED
- priv->led_packets += len;
- iwl4965_setup_activity_timer(priv);
-#endif
}
/* Calc max signal level (dBm) among 3 possible receivers */
return 0;
}
-void iwl4965_init_ht_hw_capab(struct ieee80211_ht_info *ht_info,
+void iwl4965_init_ht_hw_capab(struct iwl_priv *priv,
+ struct ieee80211_ht_info *ht_info,
enum ieee80211_band band)
{
ht_info->cap = 0;
ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_20;
ht_info->cap |= (u16)(IEEE80211_HT_CAP_MIMO_PS &
(IWL_MIMO_PS_NONE << 2));
- if (iwl4965_mod_params.amsdu_size_8K) {
- printk(KERN_DEBUG "iwl4965 in A-MSDU 8K support mode\n");
+
+ if (priv->cfg->mod_params->amsdu_size_8K)
ht_info->cap |= (u16)IEEE80211_HT_CAP_MAX_AMSDU;
- }
ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
-/* Called for REPLY_4965_RX (legacy ABG frames), or
+/* Called for REPLY_RX (legacy ABG frames), or
* REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
static void iwl4965_rx_reply_rx(struct iwl_priv *priv,
struct iwl4965_rx_mem_buffer *rxb)
/* Use phy data (Rx signal strength, etc.) contained within
* this rx packet for legacy frames,
* or phy data cached from REPLY_RX_PHY_CMD for HT frames. */
- int include_phy = (pkt->hdr.cmd == REPLY_4965_RX);
+ int include_phy = (pkt->hdr.cmd == REPLY_RX);
struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
(struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) :
(struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
{
/* Simply stop the queue, but don't change any configuration;
* the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
- iwl4965_write_prph(priv,
+ iwl_write_prph(priv,
KDR_SCD_QUEUE_STATUS_BITS(txq_id),
(0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
(1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
return -EINVAL;
}
- ret = iwl4965_grab_nic_access(priv);
+ ret = iwl_grab_nic_access(priv);
if (ret)
return ret;
iwl4965_tx_queue_stop_scheduler(priv, txq_id);
- iwl4965_clear_bits_prph(priv, KDR_SCD_QUEUECHAIN_SEL, (1 << txq_id));
+ iwl_clear_bits_prph(priv, KDR_SCD_QUEUECHAIN_SEL, (1 << txq_id));
priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
/* supposes that ssn_idx is valid (!= 0xFFF) */
iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
- iwl4965_clear_bits_prph(priv, KDR_SCD_INTERRUPT_MASK, (1 << txq_id));
+ iwl_clear_bits_prph(priv, KDR_SCD_INTERRUPT_MASK, (1 << txq_id));
iwl4965_txq_ctx_deactivate(priv, txq_id);
iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
- iwl4965_release_nic_access(priv);
+ iwl_release_nic_access(priv);
return 0;
}
tbl_dw_addr = priv->scd_base_addr +
SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
- tbl_dw = iwl4965_read_targ_mem(priv, tbl_dw_addr);
+ tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
if (txq_id & 0x1)
tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
else
tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
- iwl4965_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
+ iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
return 0;
}
iwl4965_sta_modify_enable_tid_tx(priv, sta_id, tid);
spin_lock_irqsave(&priv->lock, flags);
- rc = iwl4965_grab_nic_access(priv);
+ rc = iwl_grab_nic_access(priv);
if (rc) {
spin_unlock_irqrestore(&priv->lock, flags);
return rc;
iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
/* Set this queue as a chain-building queue */
- iwl4965_set_bits_prph(priv, KDR_SCD_QUEUECHAIN_SEL, (1 << txq_id));
+ iwl_set_bits_prph(priv, KDR_SCD_QUEUECHAIN_SEL, (1 << txq_id));
/* Place first TFD at index corresponding to start sequence number.
* Assumes that ssn_idx is valid (!= 0xFFF) */
iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
/* Set up Tx window size and frame limit for this queue */
- iwl4965_write_targ_mem(priv,
+ iwl_write_targ_mem(priv,
priv->scd_base_addr + SCD_CONTEXT_QUEUE_OFFSET(txq_id),
(SCD_WIN_SIZE << SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
- iwl4965_write_targ_mem(priv, priv->scd_base_addr +
+ iwl_write_targ_mem(priv, priv->scd_base_addr +
SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
(SCD_FRAME_LIMIT << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
& SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
- iwl4965_set_bits_prph(priv, KDR_SCD_INTERRUPT_MASK, (1 << txq_id));
+ iwl_set_bits_prph(priv, KDR_SCD_INTERRUPT_MASK, (1 << txq_id));
/* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
- iwl4965_release_nic_access(priv);
+ iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
return 0;
/* Update the rate scaling for control frame Tx to AP */
link_cmd.sta_id = is_ap ? IWL_AP_ID : priv->hw_setting.bcast_sta_id;
- iwl4965_send_cmd_pdu(priv, REPLY_TX_LINK_QUALITY_CMD, sizeof(link_cmd),
+ iwl_send_cmd_pdu(priv, REPLY_TX_LINK_QUALITY_CMD, sizeof(link_cmd),
&link_cmd);
}
{
const struct iwl_channel_info *ch_info;
- ch_info = iwl4965_get_channel_info(priv, band, channel);
+ ch_info = iwl_get_channel_info(priv, band, channel);
if (!is_channel_valid(ch_info))
return 0;
void iwl4965_hw_rx_handler_setup(struct iwl_priv *priv)
{
/* Legacy Rx frames */
- priv->rx_handlers[REPLY_4965_RX] = iwl4965_rx_reply_rx;
+ priv->rx_handlers[REPLY_RX] = iwl4965_rx_reply_rx;
/* High-throughput (HT) Rx frames */
priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl4965_rx_reply_rx_phy;
cancel_delayed_work(&priv->init_alive_start);
}
+static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
+ .enqueue_hcmd = iwl4965_enqueue_hcmd,
+};
+
static struct iwl_lib_ops iwl4965_lib = {
.init_drv = iwl4965_init_drv,
.eeprom_ops = {
static struct iwl_ops iwl4965_ops = {
.lib = &iwl4965_lib,
+ .utils = &iwl4965_hcmd_utils,
};
static struct iwl_cfg iwl4965_agn_cfg = {
.fw_name = "iwlwifi-4965" IWL4965_UCODE_API ".ucode",
.sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
.ops = &iwl4965_ops,
+ .mod_params = &iwl4965_mod_params,
};
struct pci_device_id iwl4965_hw_card_ids[] = {
};
MODULE_DEVICE_TABLE(pci, iwl4965_hw_card_ids);
+
+module_param_named(antenna, iwl4965_mod_params.antenna, int, 0444);
+MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
+module_param_named(disable, iwl4965_mod_params.disable, int, 0444);
+MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
+module_param_named(hwcrypto, iwl4965_mod_params.hw_crypto, int, 0444);
+MODULE_PARM_DESC(hwcrypto,
+ "using hardware crypto engine (default 0 [software])\n");
+module_param_named(debug, iwl4965_mod_params.debug, int, 0444);
+MODULE_PARM_DESC(debug, "debug output mask");
+module_param_named(
+ disable_hw_scan, iwl4965_mod_params.disable_hw_scan, int, 0444);
+MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
+
+module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, 0444);
+MODULE_PARM_DESC(queues_num, "number of hw queues.");
+
+/* QoS */
+module_param_named(qos_enable, iwl4965_mod_params.enable_qos, int, 0444);
+MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
+module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K, int, 0444);
+MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
+
projects / deliverable / linux.git / blobdiff