iwlagn: all function iwl-io.c receive iwl_bus

[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-eeprom.c

diff --git a/drivers/net/wireless/iwlwifi/iwl-eeprom.c b/drivers/net/wireless/iwlwifi/iwl-eeprom.c
index 19d31a5e32e5269032f2c3f06d12c294c8a1ca7d..80ee65be9cd19b1db9f3f395bfea2bdc40a66941 100644 (file)
--- a/drivers/net/wireless/iwlwifi/iwl-eeprom.c
+++ b/drivers/net/wireless/iwlwifi/iwl-eeprom.c
@@ -155,11 +155,11 @@ static int iwl_eeprom_acquire_semaphore(struct iwl_priv *priv)
 
        for (count = 0; count < EEPROM_SEM_RETRY_LIMIT; count++) {
                /* Request semaphore */
-               iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
+               iwl_set_bit(bus(priv), CSR_HW_IF_CONFIG_REG,
                            CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
 
                /* See if we got it */
-               ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
+               ret = iwl_poll_bit(bus(priv), CSR_HW_IF_CONFIG_REG,
                                CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
                                CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
                                EEPROM_SEM_TIMEOUT);
@@ -176,14 +176,14 @@ static int iwl_eeprom_acquire_semaphore(struct iwl_priv *priv)
 
 static void iwl_eeprom_release_semaphore(struct iwl_priv *priv)
 {
-       iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
+       iwl_clear_bit(bus(priv), CSR_HW_IF_CONFIG_REG,
                CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
 
 }
 
 static int iwl_eeprom_verify_signature(struct iwl_priv *priv)
 {
-       u32 gp = iwl_read32(priv, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK;
+       u32 gp = iwl_read32(bus(priv), CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK;
        int ret = 0;
 
        IWL_DEBUG_EEPROM(priv, "EEPROM signature=0x%08x\n", gp);
@@ -216,17 +216,17 @@ static int iwl_eeprom_verify_signature(struct iwl_priv *priv)
 
 static void iwl_set_otp_access(struct iwl_priv *priv, enum iwl_access_mode mode)
 {
-       iwl_read32(priv, CSR_OTP_GP_REG);
+       iwl_read32(bus(priv), CSR_OTP_GP_REG);
 
        if (mode == IWL_OTP_ACCESS_ABSOLUTE)
-               iwl_clear_bit(priv, CSR_OTP_GP_REG,
+               iwl_clear_bit(bus(priv), CSR_OTP_GP_REG,
                              CSR_OTP_GP_REG_OTP_ACCESS_MODE);
        else
-               iwl_set_bit(priv, CSR_OTP_GP_REG,
+               iwl_set_bit(bus(priv), CSR_OTP_GP_REG,
                            CSR_OTP_GP_REG_OTP_ACCESS_MODE);
 }
 
-static int iwlcore_get_nvm_type(struct iwl_priv *priv, u32 hw_rev)
+static int iwl_get_nvm_type(struct iwl_priv *priv, u32 hw_rev)
 {
        u32 otpgp;
        int nvm_type;
@@ -243,7 +243,7 @@ static int iwlcore_get_nvm_type(struct iwl_priv *priv, u32 hw_rev)
                nvm_type = NVM_DEVICE_TYPE_EEPROM;
                break;
        default:
-               otpgp = iwl_read32(priv, CSR_OTP_GP_REG);
+               otpgp = iwl_read32(bus(priv), CSR_OTP_GP_REG);
                if (otpgp & CSR_OTP_GP_REG_DEVICE_SELECT)
                        nvm_type = NVM_DEVICE_TYPE_OTP;
                else
@@ -258,22 +258,22 @@ static int iwl_init_otp_access(struct iwl_priv *priv)
        int ret;
 
        /* Enable 40MHz radio clock */
-       iwl_write32(priv, CSR_GP_CNTRL,
-                   iwl_read32(priv, CSR_GP_CNTRL) |
+       iwl_write32(bus(priv), CSR_GP_CNTRL,
+                   iwl_read32(bus(priv), CSR_GP_CNTRL) |
                    CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 
        /* wait for clock to be ready */
-       ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
+       ret = iwl_poll_bit(bus(priv), CSR_GP_CNTRL,
                                 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
                                 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
                                 25000);
        if (ret < 0)
                IWL_ERR(priv, "Time out access OTP\n");
        else {
-               iwl_set_bits_prph(priv, APMG_PS_CTRL_REG,
+               iwl_set_bits_prph(bus(priv), APMG_PS_CTRL_REG,
                                  APMG_PS_CTRL_VAL_RESET_REQ);
                udelay(5);
-               iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
+               iwl_clear_bits_prph(bus(priv), APMG_PS_CTRL_REG,
                                    APMG_PS_CTRL_VAL_RESET_REQ);
 
                /*
@@ -281,7 +281,7 @@ static int iwl_init_otp_access(struct iwl_priv *priv)
                 * this is only applicable for HW with OTP shadow RAM
                 */
                if (priv->cfg->base_params->shadow_ram_support)
-                       iwl_set_bit(priv, CSR_DBG_LINK_PWR_MGMT_REG,
+                       iwl_set_bit(bus(priv), CSR_DBG_LINK_PWR_MGMT_REG,
                                CSR_RESET_LINK_PWR_MGMT_DISABLED);
        }
        return ret;
@@ -293,9 +293,9 @@ static int iwl_read_otp_word(struct iwl_priv *priv, u16 addr, __le16 *eeprom_dat
        u32 r;
        u32 otpgp;
 
-       iwl_write32(priv, CSR_EEPROM_REG,
+       iwl_write32(bus(priv), CSR_EEPROM_REG,
                    CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
-       ret = iwl_poll_bit(priv, CSR_EEPROM_REG,
+       ret = iwl_poll_bit(bus(priv), CSR_EEPROM_REG,
                                 CSR_EEPROM_REG_READ_VALID_MSK,
                                 CSR_EEPROM_REG_READ_VALID_MSK,
                                 IWL_EEPROM_ACCESS_TIMEOUT);
@@ -303,13 +303,13 @@ static int iwl_read_otp_word(struct iwl_priv *priv, u16 addr, __le16 *eeprom_dat
                IWL_ERR(priv, "Time out reading OTP[%d]\n", addr);
                return ret;
        }
-       r = iwl_read32(priv, CSR_EEPROM_REG);
+       r = iwl_read32(bus(priv), CSR_EEPROM_REG);
        /* check for ECC errors: */
-       otpgp = iwl_read32(priv, CSR_OTP_GP_REG);
+       otpgp = iwl_read32(bus(priv), CSR_OTP_GP_REG);
        if (otpgp & CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK) {
                /* stop in this case */
                /* set the uncorrectable OTP ECC bit for acknowledgement */
-               iwl_set_bit(priv, CSR_OTP_GP_REG,
+               iwl_set_bit(bus(priv), CSR_OTP_GP_REG,
                        CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
                IWL_ERR(priv, "Uncorrectable OTP ECC error, abort OTP read\n");
                return -EINVAL;
@@ -317,7 +317,7 @@ static int iwl_read_otp_word(struct iwl_priv *priv, u16 addr, __le16 *eeprom_dat
        if (otpgp & CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK) {
                /* continue in this case */
                /* set the correctable OTP ECC bit for acknowledgement */
-               iwl_set_bit(priv, CSR_OTP_GP_REG,
+               iwl_set_bit(bus(priv), CSR_OTP_GP_REG,
                                CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK);
                IWL_ERR(priv, "Correctable OTP ECC error, continue read\n");
        }
@@ -424,14 +424,14 @@ u16 iwl_eeprom_query16(const struct iwl_priv *priv, size_t offset)
 int iwl_eeprom_init(struct iwl_priv *priv, u32 hw_rev)
 {
        __le16 *e;
-       u32 gp = iwl_read32(priv, CSR_EEPROM_GP);
+       u32 gp = iwl_read32(bus(priv), CSR_EEPROM_GP);
        int sz;
        int ret;
        u16 addr;
        u16 validblockaddr = 0;
        u16 cache_addr = 0;
 
-       priv->nvm_device_type = iwlcore_get_nvm_type(priv, hw_rev);
+       priv->nvm_device_type = iwl_get_nvm_type(priv, hw_rev);
        if (priv->nvm_device_type == -ENOENT)
                return -ENOENT;
        /* allocate eeprom */
@@ -469,11 +469,11 @@ int iwl_eeprom_init(struct iwl_priv *priv, u32 hw_rev)
                        ret = -ENOENT;
                        goto done;
                }
-               iwl_write32(priv, CSR_EEPROM_GP,
-                           iwl_read32(priv, CSR_EEPROM_GP) &
+               iwl_write32(bus(priv), CSR_EEPROM_GP,
+                           iwl_read32(bus(priv), CSR_EEPROM_GP) &
                            ~CSR_EEPROM_GP_IF_OWNER_MSK);
 
-               iwl_set_bit(priv, CSR_OTP_GP_REG,
+               iwl_set_bit(bus(priv), CSR_OTP_GP_REG,
                             CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK |
                             CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
                /* traversing the linked list if no shadow ram supported */
@@ -498,10 +498,10 @@ int iwl_eeprom_init(struct iwl_priv *priv, u32 hw_rev)
                for (addr = 0; addr < sz; addr += sizeof(u16)) {
                        u32 r;
 
-                       iwl_write32(priv, CSR_EEPROM_REG,
+                       iwl_write32(bus(priv), CSR_EEPROM_REG,
                                    CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
 
-                       ret = iwl_poll_bit(priv, CSR_EEPROM_REG,
+                       ret = iwl_poll_bit(bus(priv), CSR_EEPROM_REG,
                                                  CSR_EEPROM_REG_READ_VALID_MSK,
                                                  CSR_EEPROM_REG_READ_VALID_MSK,
                                                  IWL_EEPROM_ACCESS_TIMEOUT);
@@ -509,7 +509,7 @@ int iwl_eeprom_init(struct iwl_priv *priv, u32 hw_rev)
                                IWL_ERR(priv, "Time out reading EEPROM[%d]\n", addr);
                                goto done;
                        }
-                       r = iwl_read32(priv, CSR_EEPROM_REG);
+                       r = iwl_read32(bus(priv), CSR_EEPROM_REG);
                        e[addr / 2] = cpu_to_le16(r >> 16);
                }
        }
@@ -838,7 +838,7 @@ void iwl_rf_config(struct iwl_priv *priv)
 
        /* write radio config values to register */
        if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) <= EEPROM_RF_CONFIG_TYPE_MAX) {
-               iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
+               iwl_set_bit(bus(priv), CSR_HW_IF_CONFIG_REG,
                            EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
                            EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
                            EEPROM_RF_CFG_DASH_MSK(radio_cfg));
@@ -850,7 +850,7 @@ void iwl_rf_config(struct iwl_priv *priv)
                WARN_ON(1);
 
        /* set CSR_HW_CONFIG_REG for uCode use */
-       iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
+       iwl_set_bit(bus(priv), CSR_HW_IF_CONFIG_REG,
                    CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
                    CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
 }