return 0;
}
+MODULE_FIRMWARE("mwl8k/helper_8687.fw");
+MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
+
struct mwl8k_cmd_pkt {
__le16 code;
__le16 length;
#define MWL8K_PEER_TYPE_ACCESSPOINT 2
#define MWL8K_IEEE_LEGACY_DATA_RATES 13
-#define MWL8K_MCS_BITMAP_SIZE 16
struct peer_capability_info {
/* Peer type - AP vs. STA. */
__u8 legacy_rates[MWL8K_IEEE_LEGACY_DATA_RATES];
/* HT rate table. Intersection of our rates and peer rates. */
- __u8 ht_rates[MWL8K_MCS_BITMAP_SIZE];
+ __u8 ht_rates[16];
__u8 pad[16];
/* If set, interoperability mode, no proprietary extensions. */
/*
- * Packet reception.
+ * Packet reception for 88w8366.
+ */
+struct mwl8k_rxd_8366 {
+ __le16 pkt_len;
+ __u8 sq2;
+ __u8 rate;
+ __le32 pkt_phys_addr;
+ __le32 next_rxd_phys_addr;
+ __le16 qos_control;
+ __le16 htsig2;
+ __le32 hw_rssi_info;
+ __le32 hw_noise_floor_info;
+ __u8 noise_floor;
+ __u8 pad0[3];
+ __u8 rssi;
+ __u8 rx_status;
+ __u8 channel;
+ __u8 rx_ctrl;
+} __attribute__((packed));
+
+#define MWL8K_8366_RX_CTRL_OWNED_BY_HOST 0x80
+
+static void mwl8k_rxd_8366_init(void *_rxd, dma_addr_t next_dma_addr)
+{
+ struct mwl8k_rxd_8366 *rxd = _rxd;
+
+ rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
+ rxd->rx_ctrl = MWL8K_8366_RX_CTRL_OWNED_BY_HOST;
+}
+
+static void mwl8k_rxd_8366_refill(void *_rxd, dma_addr_t addr, int len)
+{
+ struct mwl8k_rxd_8366 *rxd = _rxd;
+
+ rxd->pkt_len = cpu_to_le16(len);
+ rxd->pkt_phys_addr = cpu_to_le32(addr);
+ wmb();
+ rxd->rx_ctrl = 0;
+}
+
+static int
+mwl8k_rxd_8366_process(void *_rxd, struct ieee80211_rx_status *status)
+{
+ struct mwl8k_rxd_8366 *rxd = _rxd;
+
+ if (!(rxd->rx_ctrl & MWL8K_8366_RX_CTRL_OWNED_BY_HOST))
+ return -1;
+ rmb();
+
+ memset(status, 0, sizeof(*status));
+
+ status->signal = -rxd->rssi;
+ status->noise = -rxd->noise_floor;
+
+ if (rxd->rate & 0x80) {
+ status->flag |= RX_FLAG_HT;
+ status->rate_idx = rxd->rate & 0x7f;
+ } else {
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(mwl8k_rates); i++) {
+ if (mwl8k_rates[i].hw_value == rxd->rate) {
+ status->rate_idx = i;
+ break;
+ }
+ }
+ }
+
+ status->band = IEEE80211_BAND_2GHZ;
+ status->freq = ieee80211_channel_to_frequency(rxd->channel);
+
+ return le16_to_cpu(rxd->pkt_len);
+}
+
+static struct rxd_ops rxd_8366_ops = {
+ .rxd_size = sizeof(struct mwl8k_rxd_8366),
+ .rxd_init = mwl8k_rxd_8366_init,
+ .rxd_refill = mwl8k_rxd_8366_refill,
+ .rxd_process = mwl8k_rxd_8366_process,
+};
+
+/*
+ * Packet reception for 88w8687.
*/
struct mwl8k_rxd_8687 {
__le16 pkt_len;
*/
struct mwl8k_cmd_set_mac_addr {
struct mwl8k_cmd_pkt header;
- __u8 mac_addr[ETH_ALEN];
+ union {
+ struct {
+ __le16 mac_type;
+ __u8 mac_addr[ETH_ALEN];
+ } mbss;
+ __u8 mac_addr[ETH_ALEN];
+ };
} __attribute__((packed));
static int mwl8k_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
{
+ struct mwl8k_priv *priv = hw->priv;
struct mwl8k_cmd_set_mac_addr *cmd;
int rc;
cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
cmd->header.length = cpu_to_le16(sizeof(*cmd));
- memcpy(cmd->mac_addr, mac, ETH_ALEN);
+ if (priv->ap_fw) {
+ cmd->mbss.mac_type = 0;
+ memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
+ } else {
+ memcpy(cmd->mac_addr, mac, ETH_ALEN);
+ }
rc = mwl8k_post_cmd(hw, &cmd->header);
kfree(cmd);
/* TX opportunity in units of 32 us */
__le16 txop;
- /* Log exponent of max contention period: 0...15*/
- __u8 log_cw_max;
+ union {
+ struct {
+ /* Log exponent of max contention period: 0...15 */
+ __le32 log_cw_max;
+
+ /* Log exponent of min contention period: 0...15 */
+ __le32 log_cw_min;
- /* Log exponent of min contention period: 0...15 */
- __u8 log_cw_min;
+ /* Adaptive interframe spacing in units of 32us */
+ __u8 aifs;
- /* Adaptive interframe spacing in units of 32us */
- __u8 aifs;
+ /* TX queue to configure */
+ __u8 txq;
+ } ap;
+ struct {
+ /* Log exponent of max contention period: 0...15 */
+ __u8 log_cw_max;
- /* TX queue to configure */
- __u8 txq;
+ /* Log exponent of min contention period: 0...15 */
+ __u8 log_cw_min;
+
+ /* Adaptive interframe spacing in units of 32us */
+ __u8 aifs;
+
+ /* TX queue to configure */
+ __u8 txq;
+ } sta;
+ };
} __attribute__((packed));
#define MWL8K_SET_EDCA_CW 0x01
__u16 cw_min, __u16 cw_max,
__u8 aifs, __u16 txop)
{
+ struct mwl8k_priv *priv = hw->priv;
struct mwl8k_cmd_set_edca_params *cmd;
int rc;
cmd->header.length = cpu_to_le16(sizeof(*cmd));
cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
cmd->txop = cpu_to_le16(txop);
- cmd->log_cw_max = (u8)ilog2(cw_max + 1);
- cmd->log_cw_min = (u8)ilog2(cw_min + 1);
- cmd->aifs = aifs;
- cmd->txq = qnum;
+ if (priv->ap_fw) {
+ cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
+ cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
+ cmd->ap.aifs = aifs;
+ cmd->ap.txq = qnum;
+ } else {
+ cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
+ cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
+ cmd->sta.aifs = aifs;
+ cmd->sta.txq = qnum;
+ }
rc = mwl8k_post_cmd(hw, &cmd->header);
kfree(cmd);
__u8 legacy_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
/* Bitmap for supported MCS codes. */
- __u8 mcs_set[MWL8K_IEEE_LEGACY_DATA_RATES];
- __u8 reserved[MWL8K_IEEE_LEGACY_DATA_RATES];
+ __u8 mcs_set[16];
+ __u8 reserved[16];
} __attribute__((packed));
static int mwl8k_update_rateset(struct ieee80211_hw *hw,
struct mwl8k_priv *priv = hw->priv;
int rc;
- rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
+ rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
IRQF_SHARED, MWL8K_NAME, hw);
if (rc) {
printk(KERN_ERR "%s: failed to register IRQ handler\n",
priv->beacon_skb = NULL;
}
-static struct mwl8k_device_info di_8687 = {
- .part_name = "88w8687",
- .helper_image = "mwl8k/helper_8687.fw",
- .fw_image = "mwl8k/fmimage_8687.fw",
- .rxd_ops = &rxd_8687_ops,
- .modes = BIT(NL80211_IFTYPE_STATION),
+enum {
+ MWL8687 = 0,
+ MWL8366,
};
-static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
+static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = {
+ {
+ .part_name = "88w8687",
+ .helper_image = "mwl8k/helper_8687.fw",
+ .fw_image = "mwl8k/fmimage_8687.fw",
+ .rxd_ops = &rxd_8687_ops,
+ .modes = BIT(NL80211_IFTYPE_STATION),
+ },
{
- PCI_VDEVICE(MARVELL, 0x2a2b),
- .driver_data = (unsigned long)&di_8687,
- }, {
- PCI_VDEVICE(MARVELL, 0x2a30),
- .driver_data = (unsigned long)&di_8687,
- }, {
+ .part_name = "88w8366",
+ .helper_image = "mwl8k/helper_8366.fw",
+ .fw_image = "mwl8k/fmimage_8366.fw",
+ .rxd_ops = &rxd_8366_ops,
+ .modes = 0,
},
};
+
+static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
+ { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
+ { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
+ { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
+ { },
+};
MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
static int __devinit mwl8k_probe(struct pci_dev *pdev,
priv = hw->priv;
priv->hw = hw;
priv->pdev = pdev;
- priv->device_info = (void *)id->driver_data;
+ priv->device_info = &mwl8k_info_tbl[id->driver_data];
priv->rxd_ops = priv->device_info->rxd_ops;
priv->sniffer_enabled = false;
priv->wmm_enabled = false;
iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
- rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
+ rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
IRQF_SHARED, MWL8K_NAME, hw);
if (rc) {
printk(KERN_ERR "%s: failed to register IRQ handler\n",
projects / deliverable / linux.git / blobdiff