Merge branch 'pci/host-hv' into next

[deliverable/linux.git] / drivers / pci / probe.c

diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 1e34d211389a2dbd902a2e206a8fec6a88b88193..c4e1eff8b07c27aa4b6d7b8a31a2e7c5d8795f46 100644 (file)
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -16,7 +16,6 @@
 #include <linux/aer.h>
 #include <linux/acpi.h>
 #include <linux/irqdomain.h>
-#include <asm-generic/pci-bridge.h>
 #include "pci.h"
 
 #define CARDBUS_LATENCY_TIMER  176     /* secondary latency timer */
@@ -773,6 +772,12 @@ add_dev:
 
        pcibios_add_bus(child);
 
+       if (child->ops->add_bus) {
+               ret = child->ops->add_bus(child);
+               if (WARN_ON(ret < 0))
+                       dev_err(&child->dev, "failed to add bus: %d\n", ret);
+       }
+
        /* Create legacy_io and legacy_mem files for this bus */
        pci_create_legacy_files(child);
 
@@ -1623,7 +1628,7 @@ static void pci_init_capabilities(struct pci_dev *dev)
        pci_pm_init(dev);
 
        /* Vital Product Data */
-       pci_vpd_pci22_init(dev);
+       pci_vpd_init(dev);
 
        /* Alternative Routing-ID Forwarding */
        pci_configure_ari(dev);
@@ -1818,6 +1823,13 @@ static int only_one_child(struct pci_bus *bus)
                return 0;
        if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
                return 1;
+
+       /*
+        * PCIe downstream ports are bridges that normally lead to only a
+        * device 0, but if PCI_SCAN_ALL_PCIE_DEVS is set, scan all
+        * possible devices, not just device 0.  See PCIe spec r3.0,
+        * sec 7.3.1.
+        */
        if (parent->has_secondary_link &&
            !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
                return 1;