/* GPIO Registers */
#define INPUT_VALUE 0x00
+#define OUTPUT_EN 0x04
#define IRQ_PENDING 0x0c
#define OUTPUT_SET 0x14
#define OUTPUT_CLEAR 0x18
.get_group_name = oxnas_pinctrl_get_group_name,
.get_group_pins = oxnas_pinctrl_get_group_pins,
.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
- .dt_free_map = pinctrl_utils_dt_free_map,
+ .dt_free_map = pinctrl_utils_free_map,
};
static int oxnas_pinmux_get_functions_count(struct pinctrl_dev *pctldev)
return 0;
}
+static int oxnas_gpio_get_direction(struct gpio_chip *chip,
+ unsigned int offset)
+{
+ struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
+ u32 mask = BIT(offset);
+
+ return !(readl_relaxed(bank->reg_base + OUTPUT_EN) & mask);
+}
+
static int oxnas_gpio_direction_input(struct gpio_chip *chip,
unsigned int offset)
{
.label = "GPIO" #_bank, \
.request = gpiochip_generic_request, \
.free = gpiochip_generic_free, \
+ .get_direction = oxnas_gpio_get_direction, \
.direction_input = oxnas_gpio_direction_input, \
.direction_output = oxnas_gpio_direction_output, \
.get = oxnas_gpio_get, \