Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/sage/ceph...
[deliverable/linux.git] / drivers / scsi / hpsa_cmd.h
index dfdb4a5c36466c11910f11fc044d7231c3d392fc..b5cc7052339f91ed3f157c28c836a6788d433b68 100644 (file)
@@ -1,6 +1,6 @@
 /*
  *    Disk Array driver for HP Smart Array SAS controllers
- *    Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
+ *    Copyright 2000, 2014 Hewlett-Packard Development Company, L.P.
  *
  *    This program is free software; you can redistribute it and/or modify
  *    it under the terms of the GNU General Public License as published by
@@ -82,8 +82,9 @@
 #define ATTR_ACA                0x07
 
 /* cdb type */
-#define TYPE_CMD                               0x00
-#define TYPE_MSG                               0x01
+#define TYPE_CMD               0x00
+#define TYPE_MSG               0x01
+#define TYPE_IOACCEL2_CMD      0x81 /* 0x81 is not used by hardware */
 
 /* Message Types  */
 #define HPSA_TASK_MANAGEMENT    0x00
 #define CFGTBL_BusType_Fibre2G  0x00000200l
 
 /* VPD Inquiry types */
+#define HPSA_VPD_SUPPORTED_PAGES        0x00
 #define HPSA_VPD_LV_DEVICE_GEOMETRY     0xC1
 #define HPSA_VPD_LV_IOACCEL_STATUS      0xC2
+#define HPSA_VPD_LV_STATUS             0xC3
+#define HPSA_VPD_HEADER_SZ              4
+
+/* Logical volume states */
+#define HPSA_VPD_LV_STATUS_UNSUPPORTED                 -1
+#define HPSA_LV_OK                                      0x0
+#define HPSA_LV_UNDERGOING_ERASE                       0x0F
+#define HPSA_LV_UNDERGOING_RPI                         0x12
+#define HPSA_LV_PENDING_RPI                            0x13
+#define HPSA_LV_ENCRYPTED_NO_KEY                       0x14
+#define HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER   0x15
+#define HPSA_LV_UNDERGOING_ENCRYPTION                  0x16
+#define HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING         0x17
+#define HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER  0x18
+#define HPSA_LV_PENDING_ENCRYPTION                     0x19
+#define HPSA_LV_PENDING_ENCRYPTION_REKEYING            0x1A
 
 struct vals32 {
        u32   lower;
@@ -206,7 +224,10 @@ struct raid_map_data {
        u16   row_cnt;                  /* rows in each layout map */
        u16   layout_map_count;         /* layout maps (1 map per mirror/parity
                                         * group) */
-       u8    reserved[20];
+       u16   flags;                    /* Bit 0 set if encryption enabled */
+#define RAID_MAP_FLAG_ENCRYPT_ON  0x01
+       u16   dekindex;                 /* Data encryption key index. */
+       u8    reserved[16];
        struct raid_map_disk_data data[RAID_MAP_MAX_ENTRIES];
 };
 
@@ -236,6 +257,7 @@ struct SenseSubsystem_info {
 #define BMIC_CACHE_FLUSH 0xc2
 #define HPSA_CACHE_FLUSH 0x01  /* C2 was already being used by HPSA */
 #define BMIC_FLASH_FIRMWARE 0xF7
+#define BMIC_SENSE_CONTROLLER_PARAMETERS 0x64
 
 /* Command List Structure */
 union SCSI3Addr {
@@ -365,7 +387,6 @@ struct CommandList {
        int                        cmd_type;
        long                       cmdindex;
        struct list_head list;
-       struct request *rq;
        struct completion *waiting;
        void   *scsi_cmd;
 
@@ -378,8 +399,8 @@ struct CommandList {
  */
 #define IS_32_BIT ((8 - sizeof(long))/4)
 #define IS_64_BIT (!IS_32_BIT)
-#define PAD_32 (36)
-#define PAD_64 (4)
+#define PAD_32 (40)
+#define PAD_64 (12)
 #define COMMANDLIST_PAD (IS_32_BIT * PAD_32 + IS_64_BIT * PAD_64)
        u8 pad[COMMANDLIST_PAD];
 };
@@ -478,6 +499,7 @@ struct io_accel2_scsi_response {
 #define IOACCEL2_STATUS_SR_TASK_COMP_RES_CON   0x18
 #define IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL  0x28
 #define IOACCEL2_STATUS_SR_TASK_COMP_ABORTED   0x40
+#define IOACCEL2_STATUS_SR_IOACCEL_DISABLED    0x0E
        u8 data_present;                /* low 2 bits */
 #define IOACCEL2_NO_DATAPRESENT                0x000
 #define IOACCEL2_RESPONSE_DATAPRESENT  0x001
@@ -498,11 +520,17 @@ struct io_accel2_scsi_response {
  */
 struct io_accel2_cmd {
        u8  IU_type;                    /* IU Type */
-       u8  direction;                  /* Transfer direction, 2 bits */
+       u8  direction;                  /* direction, memtype, and encryption */
+#define IOACCEL2_DIRECTION_MASK                0x03 /* bits 0,1: direction  */
+#define IOACCEL2_DIRECTION_MEMTYPE_MASK        0x04 /* bit 2: memtype source/dest */
+                                            /*     0b=PCIe, 1b=DDR */
+#define IOACCEL2_DIRECTION_ENCRYPT_MASK        0x08 /* bit 3: encryption flag */
+                                            /*     0=off, 1=on */
        u8  reply_queue;                /* Reply Queue ID */
        u8  reserved1;                  /* Reserved */
        u32 scsi_nexus;                 /* Device Handle */
-       struct vals32 Tag;              /* cciss tag */
+       u32 Tag;                        /* cciss tag, lower 4 bytes only */
+       u32 tweak_lower;                /* Encryption tweak, lower 4 bytes */
        u8  cdb[16];                    /* SCSI Command Descriptor Block */
        u8  cciss_lun[8];               /* 8 byte SCSI address */
        u32 data_len;                   /* Total bytes to transfer */
@@ -510,10 +538,10 @@ struct io_accel2_cmd {
 #define IOACCEL2_PRIORITY_MASK 0x78
 #define IOACCEL2_ATTR_MASK 0x07
        u8  sg_count;                   /* Number of sg elements */
-       u8  reserved3[2];               /* Reserved */
+       u16 dekindex;                   /* Data encryption key index */
        u64 err_ptr;                    /* Error Pointer */
        u32 err_len;                    /* Error Length*/
-       u8 reserved4[4];                /* Reserved */
+       u32 tweak_upper;                /* Encryption tweak, upper 4 bytes */
        struct ioaccel2_sg_element sg[IOACCEL2_MAXSGENTRIES];
        struct io_accel2_scsi_response error_data;
        u8 pad[IOACCEL2_PAD];
@@ -524,7 +552,7 @@ struct io_accel2_cmd {
  * FIXME: this can't be all I need mfm
  */
 #define IOACCEL2_IU_TYPE       0x40
-#define IU_TYPE_TMF            0x41
+#define IOACCEL2_IU_TMF_TYPE   0x41
 #define IOACCEL2_DIR_NO_DATA   0x00
 #define IOACCEL2_DIR_DATA_IN   0x01
 #define IOACCEL2_DIR_DATA_OUT  0x02
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