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staging: comedi: adv_pci_dio: use common defines for PCI-173[036] registers
[deliverable/linux.git] / drivers / staging / comedi / drivers / adv_pci_dio.c
diff --git a/drivers/staging/comedi/drivers/adv_pci_dio.c b/drivers/staging/comedi/drivers/adv_pci_dio.c
index a72b04e82ebec58adf826a89718d4683a1af514c..fae0a0b29c0312fa80aa21b0dd0ddd6ffa735ebe 100644 (file)
--- a/drivers/staging/comedi/drivers/adv_pci_dio.c
+++ b/drivers/staging/comedi/drivers/adv_pci_dio.c
@@ -48,21 +48,16 @@ enum hw_cards_id {
 #define MAX_DIO_SUBDEVG        2       /* max number of DIO subdevices group per
                                 * card */
 
-/* Register offset definitions */
-/*  Advantech PCI-1730/3/4 */
-#define        PCI1730_3_INT_EN        0x08    /* R/W: enable/disable interrupts */
-#define        PCI1730_3_INT_RF        0x0c    /* R/W: set falling/raising edge for
-                                        * interrupts */
-#define        PCI1730_3_INT_CLR       0x10    /* R/W: clear interrupts */
-
-/*  Advantech PCI-1736UP */
-#define PCI1736_3_INT_EN        0x08   /* R/W: enable/disable interrupts */
-#define PCI1736_3_INT_RF        0x0c   /* R/W: set falling/raising edge for
-                                        * interrupts */
-#define PCI1736_3_INT_CLR       0x10   /* R/W: clear interrupts */
+/*
+ * Register offset definitions
+ */
+
+/* PCI-1730, PCI-1733, PCI-1736 interrupt control registers */
+#define PCI173X_INT_EN_REG     0x08    /* R/W: enable/disable */
+#define PCI173X_INT_RF_REG     0x0c    /* R/W: falling/rising edge */
+#define PCI173X_INT_CLR_REG    0x10    /* R/W: clear */
 
 /* Advantech PCI-1739U */
-#define PCI1739_DIO       0    /* R/W: begin of 8255 registers block */
 #define PCI1739_ICR      32    /* W:   Interrupt control register */
 #define PCI1739_ISR      32    /* R:   Interrupt status register */
 
@@ -71,15 +66,12 @@ enum hw_cards_id {
 #define PCI1750_ISR      32    /* R:   Interrupt status register */
 
 /*  Advantech PCI-1751/3/3E */
-#define PCI1751_DIO       0    /* R/W: begin of 8255 registers block */
 #define PCI1751_ICR      32    /* W:   Interrupt control register */
 #define PCI1751_ISR      32    /* R:   Interrupt status register */
-#define PCI1753_DIO       0    /* R/W: begin of 8255 registers block */
 #define PCI1753_ICR0     16    /* R/W: Interrupt control register group 0 */
 #define PCI1753_ICR1     17    /* R/W: Interrupt control register group 1 */
 #define PCI1753_ICR2     18    /* R/W: Interrupt control register group 2 */
 #define PCI1753_ICR3     19    /* R/W: Interrupt control register group 3 */
-#define PCI1753E_DIO     32    /* R/W: begin of 8255 registers block */
 #define PCI1753E_ICR0    48    /* R/W: Interrupt control register group 0 */
 #define PCI1753E_ICR1    49    /* R/W: Interrupt control register group 1 */
 #define PCI1753E_ICR2    50    /* R/W: Interrupt control register group 2 */
@@ -159,7 +151,7 @@ static const struct dio_boardtype boardtypes[] = {
                .name           = "pci1739",
                .cardtype       = TYPE_PCI1739,
                .nsubdevs       = 3,
-               .sdio[0]        = { 2, PCI1739_DIO, },
+               .sdio[0]        = { 2, 0x00, },         /* 8255 DIO */
                .id_reg         = 0x08,
        },
        [TYPE_PCI1750] = {
@@ -173,7 +165,7 @@ static const struct dio_boardtype boardtypes[] = {
                .name           = "pci1751",
                .cardtype       = TYPE_PCI1751,
                .nsubdevs       = 3,
-               .sdio[0]        = { 2, PCI1751_DIO, },
+               .sdio[0]        = { 2, 0x00, },         /* 8255 DIO */
                .timer_regbase  = 0x18,
        },
        [TYPE_PCI1752] = {
@@ -189,14 +181,14 @@ static const struct dio_boardtype boardtypes[] = {
                .name           = "pci1753",
                .cardtype       = TYPE_PCI1753,
                .nsubdevs       = 4,
-               .sdio[0]        = { 4, PCI1753_DIO, },
+               .sdio[0]        = { 4, 0x00, },         /* 8255 DIO */
        },
        [TYPE_PCI1753E] = {
                .name           = "pci1753e",
                .cardtype       = TYPE_PCI1753E,
                .nsubdevs       = 8,
-               .sdio[0]        = { 4, PCI1753_DIO, },
-               .sdio[1]        = { 4, PCI1753E_DIO, },
+               .sdio[0]        = { 4, 0x00, },         /* 8255 DIO */
+               .sdio[1]        = { 4, 0x20, },         /* 8255 DIO */
        },
        [TYPE_PCI1754] = {
                .name           = "pci1754",
@@ -307,75 +299,52 @@ static int pci_dio_reset(struct comedi_device *dev)
 {
        const struct dio_boardtype *board = dev->board_ptr;
 
+       /* disable channel freeze function on the PCI-1752/1756 boards */
+       if (board->cardtype == TYPE_PCI1752 || board->cardtype == TYPE_PCI1756)
+               outw(0, dev->iobase + PCI1752_6_CFC);
+
+       /* disable and clear interrupts */
        switch (board->cardtype) {
        case TYPE_PCI1730:
        case TYPE_PCI1733:
-               /* disable interrupts */
-               outb(0, dev->iobase + PCI1730_3_INT_EN);
-               /* clear interrupts */
-               outb(0x0f, dev->iobase + PCI1730_3_INT_CLR);
-               /* set rising edge trigger */
-               outb(0, dev->iobase + PCI1730_3_INT_RF);
-               break;
-       case TYPE_PCI1734:
-               break;
-       case TYPE_PCI1735:
-               break;
-
        case TYPE_PCI1736:
-               /* disable interrupts */
-               outb(0, dev->iobase + PCI1736_3_INT_EN);
-               /* clear interrupts */
-               outb(0x0f, dev->iobase + PCI1736_3_INT_CLR);
-               /* set rising edge trigger */
-               outb(0, dev->iobase + PCI1736_3_INT_RF);
+               outb(0, dev->iobase + PCI173X_INT_EN_REG);
+               outb(0x0f, dev->iobase + PCI173X_INT_CLR_REG);
+               outb(0, dev->iobase + PCI173X_INT_RF_REG);
                break;
-
        case TYPE_PCI1739:
-               /* disable & clear interrupts */
                outb(0x88, dev->iobase + PCI1739_ICR);
                break;
-
        case TYPE_PCI1750:
        case TYPE_PCI1751:
-               /* disable & clear interrupts */
                outb(0x88, dev->iobase + PCI1750_ICR);
                break;
-       case TYPE_PCI1752:
-               outw(0, dev->iobase + PCI1752_6_CFC); /* disable channel freeze
-                                                      * function */
-               break;
        case TYPE_PCI1753E:
-               outb(0x88, dev->iobase + PCI1753E_ICR0); /* disable & clear
-                                                         * interrupts */
+               outb(0x88, dev->iobase + PCI1753E_ICR0);
                outb(0x80, dev->iobase + PCI1753E_ICR1);
                outb(0x80, dev->iobase + PCI1753E_ICR2);
                outb(0x80, dev->iobase + PCI1753E_ICR3);
                /* fallthrough */
        case TYPE_PCI1753:
-               outb(0x88, dev->iobase + PCI1753_ICR0); /* disable & clear
-                                                        * interrupts */
+               outb(0x88, dev->iobase + PCI1753_ICR0);
                outb(0x80, dev->iobase + PCI1753_ICR1);
                outb(0x80, dev->iobase + PCI1753_ICR2);
                outb(0x80, dev->iobase + PCI1753_ICR3);
                break;
        case TYPE_PCI1754:
-               outw(0x08, dev->iobase + PCI1754_6_ICR0); /* disable and clear
-                                                          * interrupts */
+               outw(0x08, dev->iobase + PCI1754_6_ICR0);
                outw(0x08, dev->iobase + PCI1754_6_ICR1);
                outw(0x08, dev->iobase + PCI1754_ICR2);
                outw(0x08, dev->iobase + PCI1754_ICR3);
                break;
        case TYPE_PCI1756:
-               outw(0, dev->iobase + PCI1752_6_CFC); /* disable channel freeze
-                                                      * function */
-               outw(0x08, dev->iobase + PCI1754_6_ICR0); /* disable and clear
-                                                          * interrupts */
+               outw(0x08, dev->iobase + PCI1754_6_ICR0);
                outw(0x08, dev->iobase + PCI1754_6_ICR1);
                break;
        case TYPE_PCI1762:
-               outw(0x0101, dev->iobase + PCI1762_ICR); /* disable & clear
-                                                         * interrupts */
+               outw(0x0101, dev->iobase + PCI1762_ICR);
+               break;
+       default:
                break;
        }
 
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