Merge tag 'for-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux...

[deliverable/linux.git] / drivers / usb / chipidea / ci.h

diff --git a/drivers/usb/chipidea/ci.h b/drivers/usb/chipidea/ci.h
index 65913d48f0c80538cb4153aeac05ee6142750191..6d6200e37b71e02b0e0d4a67cdd35f160f61de3b 100644 (file)
--- a/drivers/usb/chipidea/ci.h
+++ b/drivers/usb/chipidea/ci.h
@@ -29,6 +29,15 @@
 /******************************************************************************
  * REGISTERS
  *****************************************************************************/
+/* Identification Registers */
+#define ID_ID                          0x0
+#define ID_HWGENERAL                   0x4
+#define ID_HWHOST                      0x8
+#define ID_HWDEVICE                    0xc
+#define ID_HWTXBUF                     0x10
+#define ID_HWRXBUF                     0x14
+#define ID_SBUSCFG                     0x90
+
 /* register indices */
 enum ci_hw_regs {
        CAP_CAPLENGTH,
@@ -97,6 +106,18 @@ enum ci_role {
        CI_ROLE_END,
 };
 
+enum ci_revision {
+       CI_REVISION_1X = 10,    /* Revision 1.x */
+       CI_REVISION_20 = 20, /* Revision 2.0 */
+       CI_REVISION_21, /* Revision 2.1 */
+       CI_REVISION_22, /* Revision 2.2 */
+       CI_REVISION_23, /* Revision 2.3 */
+       CI_REVISION_24, /* Revision 2.4 */
+       CI_REVISION_25, /* Revision 2.5 */
+       CI_REVISION_25_PLUS, /* Revision above than 2.5 */
+       CI_REVISION_UNKNOWN = 99, /* Unknown Revision */
+};
+
 /**
  * struct ci_role_driver - host/gadget role driver
  * @start: start this role
@@ -141,7 +162,10 @@ struct hw_bank {
  * @role: current role
  * @is_otg: if the device is otg-capable
  * @fsm: otg finite state machine
- * @fsm_timer: pointer to timer list of otg fsm
+ * @otg_fsm_hrtimer: hrtimer for otg fsm timers
+ * @hr_timeouts: time out list for active otg fsm timers
+ * @enabled_otg_timer_bits: bits of enabled otg timers
+ * @next_otg_timer: next nearest enabled timer to be expired
  * @work: work for role changing
  * @wq: workqueue thread
  * @qh_pool: allocation pool for queue heads
@@ -169,6 +193,10 @@ struct hw_bank {
  * @b_sess_valid_event: indicates there is a vbus event, and handled
  * at ci_otg_work
  * @imx28_write_fix: Freescale imx28 needs swp instruction for writing
+ * @supports_runtime_pm: if runtime pm is supported
+ * @in_lpm: if the core in low power mode
+ * @wakeup_int: if wakeup interrupt occur
+ * @rev: The revision number for controller
  */
 struct ci_hdrc {
        struct device                   *dev;
@@ -180,7 +208,10 @@ struct ci_hdrc {
        bool                            is_otg;
        struct usb_otg                  otg;
        struct otg_fsm                  fsm;
-       struct ci_otg_fsm_timer_list    *fsm_timer;
+       struct hrtimer                  otg_fsm_hrtimer;
+       ktime_t                         hr_timeouts[NUM_OTG_FSM_TIMERS];
+       unsigned                        enabled_otg_timer_bits;
+       enum otg_fsm_timer              next_otg_timer;
        struct work_struct              work;
        struct workqueue_struct         *wq;
 
@@ -211,6 +242,10 @@ struct ci_hdrc {
        bool                            id_event;
        bool                            b_sess_valid_event;
        bool                            imx28_write_fix;
+       bool                            supports_runtime_pm;
+       bool                            in_lpm;
+       bool                            wakeup_int;
+       enum ci_revision                rev;
 };
 
 static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci)
@@ -247,6 +282,36 @@ static inline void ci_role_stop(struct ci_hdrc *ci)
        ci->roles[role]->stop(ci);
 }
 
+/**
+ * hw_read_id_reg: reads from a identification register
+ * @ci: the controller
+ * @offset: offset from the beginning of identification registers region
+ * @mask: bitfield mask
+ *
+ * This function returns register contents
+ */
+static inline u32 hw_read_id_reg(struct ci_hdrc *ci, u32 offset, u32 mask)
+{
+       return ioread32(ci->hw_bank.abs + offset) & mask;
+}
+
+/**
+ * hw_write_id_reg: writes to a identification register
+ * @ci: the controller
+ * @offset: offset from the beginning of identification registers region
+ * @mask: bitfield mask
+ * @data: new value
+ */
+static inline void hw_write_id_reg(struct ci_hdrc *ci, u32 offset,
+                           u32 mask, u32 data)
+{
+       if (~mask)
+               data = (ioread32(ci->hw_bank.abs + offset) & ~mask)
+                       | (data & mask);
+
+       iowrite32(data, ci->hw_bank.abs + offset);
+}
+
 /**
  * hw_read: reads from a hw register
  * @ci: the controller